ACM Transactions on Design Automation of Electronic Systems (TODAES)最新文献_第10页

Architectural Design of Flow-Based Microfluidic Biochips for Multi-Target Dilution of Biochemical Fluids 用于生化液体多靶点稀释的流动微流控生物芯片的结构设计

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2020-05-07 DOI: 10.1145/3357604

Nishant Kamal, Ankur Gupta, Ananya Singla, Shubham Tiwari, Parth Kohli, Sudip Roy, B. Bhattacharya

{"title":"Architectural Design of Flow-Based Microfluidic Biochips for Multi-Target Dilution of Biochemical Fluids","authors":"Nishant Kamal, Ankur Gupta, Ananya Singla, Shubham Tiwari, Parth Kohli, Sudip Roy, B. Bhattacharya","doi":"10.1145/3357604","DOIUrl":"https://doi.org/10.1145/3357604","url":null,"abstract":"Microfluidic technologies enable replacement of time-consuming and complex steps of biochemical laboratory protocols with a tiny chip. Sample preparation (i.e., dilution or mixing of fluids) is one of the primary tasks of any bioprotocol. In real-life applications where several assays need to be executed for different diagnostic purposes, the same sample fluid is often required with different target concentration factors (CFs). Although several multi-target dilution algorithms have been developed for digital microfluidic biochips, they are not efficient for implementation with continuous-flow-based microfluidic chips, which are preferred in the laboratories. In this article, we present a multi-target dilution algorithm (MTDA) for continuous-flow-based microfluidic biochips, which to the best of our knowledge is the first of its kind. We design a flow-based rotary mixer with a suitable number of segments depending on the target-CF profile, error tolerance, and optimization criteria. To schedule several intermediate fluid-mixing tasks, we develop a multi-target scheduling algorithm (MTSA) aiming to minimize the usage of storage units while producing dilutions with multiple CFs. Furthermore, we propose a storage architecture for efficiently loading (storing) of intermediate fluids from (to) the storage units.","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"43 1","pages":"1 - 34"},"PeriodicalIF":0.0,"publicationDate":"2020-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82211733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Algorithmic Fault Detection for RRAM-based Matrix Operations 基于随机存储器的矩阵运算故障检测算法

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2020-05-07 DOI: 10.1145/3386360

Mengyun Liu, Lixue Xia, Yu Wang, K. Chakrabarty

引用次数: 6

A Locality Optimizer for Loop-dominated Applications Based on Reuse Distance Analysis 基于重用距离分析的环主导应用局部优化器

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2020-05-04 DOI: 10.1145/3398189

Christakis Lezos, G. Dimitroulakos, I. Latifis, K. Masselos

引用次数: 2

Security of Microfluidic Biochip 微流控生物芯片的安全性

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2020-04-21 DOI: 10.1145/3382127

Huili Chen, S. Potluri, F. Koushanfar

引用次数: 2

An Energy-aware Online Learning Framework for Resource Management in Heterogeneous Platforms 面向异构平台资源管理的能量感知在线学习框架

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2020-03-20 DOI: 10.1145/3386359

Sumit K. Mandal, Ganapati Bhat, J. Doppa, P. Pande, Ümit Y. Ogras

{"title":"An Energy-aware Online Learning Framework for Resource Management in Heterogeneous Platforms","authors":"Sumit K. Mandal, Ganapati Bhat, J. Doppa, P. Pande, Ümit Y. Ogras","doi":"10.1145/3386359","DOIUrl":"https://doi.org/10.1145/3386359","url":null,"abstract":"Mobile platforms must satisfy the contradictory requirements of fast response time and minimum energy consumption as a function of dynamically changing applications. To address this need, systems-on-chip (SoC) that are at the heart of these devices provide a variety of control knobs, such as the number of active cores and their voltage/frequency levels. Controlling these knobs optimally at runtime is challenging for two reasons. First, the large configuration space prohibits exhaustive solutions. Second, control policies designed offline are at best sub-optimal, since many potential new applications are unknown at design-time. We address these challenges by proposing an online imitation learning approach. Our key idea is to construct an offline policy and adapt it online to new applications to optimize a given metric (e.g., energy). The proposed methodology leverages the supervision enabled by power-performance models learned at runtime. We demonstrate its effectiveness on a commercial mobile platform with 16 diverse benchmarks. Our approach successfully adapts the control policy to an unknown application after executing less than 25% of its instructions.","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"109 1","pages":"1 - 26"},"PeriodicalIF":0.0,"publicationDate":"2020-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90431142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory System 基于重用距离的受害者缓存以有效利用混合主存系统

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2020-02-28 DOI: 10.1145/3380732

Arijit Nath, Sukarn Agarwal, H. Kapoor

{"title":"Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory System","authors":"Arijit Nath, Sukarn Agarwal, H. Kapoor","doi":"10.1145/3380732","DOIUrl":"https://doi.org/10.1145/3380732","url":null,"abstract":"Hybrid main memories comprising DRAM and Non-volatile memories (NVM) are projected as potential replacements of the traditional DRAM-based memories. However, traditional cache management policies designed for improving the hit rate lack awareness of the comparative latency of read-write for NVM blocks where the write latency is more than the read latency. Therefore, developing cache management techniques that reduce costly write-backs of the NVM blocks, yet maintain a fair hit rate in the cache, is of paramount importance. We propose two techniques based on the use of a small victim cache associated with the last-level cache that helps in retaining on the chip critical DRAM and NVM blocks. Victim cache being a scarce resource, we intend to keep only performance-critical blocks in the victim cache by exploiting the idea of reuse distance. The first technique, Victim Cache Replacement Policy, works on the replacement policy of the victim cache by preferential eviction of DRAM blocks over NVM blocks. However, the second technique, Prioritized Partitioning of victim cache, logically partitions the victim cache, giving a smaller share to the DRAM blocks and a relatively larger share to the NVM blocks. Experimental evaluation on full-system simulator shows significant improvement in system performance and reduction in the number of write-backs to the NVM partition of the main memory compared to the baseline and existing technique. Additionally, NVM reads and DRAM miss rate are also improved, leading to further performance enhancement.","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"5 1","pages":"1 - 32"},"PeriodicalIF":0.0,"publicationDate":"2020-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87653137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Single-Layer Obstacle-Aware Substrate Routing via Iterative Pin Reassignment and Wire Assignment 基于迭代引脚重分配和导线分配的单层障碍物感知基板布线

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2020-02-06 DOI: 10.1145/3378162

Jin-Tai Yan

{"title":"Single-Layer Obstacle-Aware Substrate Routing via Iterative Pin Reassignment and Wire Assignment","authors":"Jin-Tai Yan","doi":"10.1145/3378162","DOIUrl":"https://doi.org/10.1145/3378162","url":null,"abstract":"It is known that single-layer obstacle-aware substrate routing is necessary for modern IC/Package designs. In this article, given a set of two-pin nets and a set of rectangular obstacles inside a single-layer routing plane, a two-phase routing algorithm including an iterative routing phase and a rip-up-and-reroute phase can be proposed to maximize the number of the routed nets in single-layer obstacle-aware substrate routing. In the iterative routing phase, based on the pin and path distribution of the routing nets and the locations of the obstacles inside a single-layer routing plane, the start or target pins on some routing nets inside dense obstacle regions may be firstly reassigned to complete the partial wiring paths on the nets. Based on the region extraction of two intersected nets in single-layer routing, the private regions of some routing nets inside sparse obstacle regions can be extracted and the nets inside the extracted regions can be further routed by using maze routing. In the rip-up-and-reroute phase, the routability of the routing nets can be improved by ripping up some routed nets and rerouting the unrouted nets. Compared with Liu's modified algorithm and Yan's flow-based algorithm in single-layer obstacle-aware substrate routing, the experimental results show that the proposed algorithm can use less CPU time to increase 3.4% and 1.8% of the routability on the routing nets for eight tested examples on the average. Additionally, the percentage of the tested examples with the 100% routability of the routing nets on the eight tested examples has been improved from 25% to 62.5%.","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"7 1","pages":"1 - 21"},"PeriodicalIF":0.0,"publicationDate":"2020-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90185396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

On Fundamental Principles for Thermal-Aware Design on Periodic Real-Time Multi-Core Systems 周期实时多核系统热感知设计的基本原理

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2020-02-06 DOI: 10.1145/3378063

Shi Sha, Ajinkya S. Bankar, Xiaokun Yang, Wujie Wen, Gang Quan

引用次数: 3

Tunable FPGA Bitstream Obfuscation with Boolean Satisfiability Attack Countermeasure 可调FPGA位流混淆与布尔可满足性攻击对策

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2020-02-03 DOI: 10.1145/3373638

Brooks Olney, Robert Karam

{"title":"Tunable FPGA Bitstream Obfuscation with Boolean Satisfiability Attack Countermeasure","authors":"Brooks Olney, Robert Karam","doi":"10.1145/3373638","DOIUrl":"https://doi.org/10.1145/3373638","url":null,"abstract":"Field Programmable Gate Arrays (FPGAs) are seeing a surge in usage in many emerging application domains, where the in-field reconfigurability is an attractive characteristic for diverse applications with dynamic design requirements, such as cloud computing, automotive, IoT, and aerospace. The security of the FPGA configuration file, or bitstream, is critical, especially for devices with long in-field lifetimes, where attackers may attempt to extract valuable Intellectual Property (IP) from within. In this article, we propose a tunable obfuscation approach that protects IP from typical bitstream attacks while enabling designers to trade off security with acceptable overhead. We also consider two potential attacks on this protection mechanism: Boolean SAT Attacks on the obfuscation and removal attacks on the protection circuitry. The obfuscation and SAT countermeasure are integrated in a custom CAD framework within a commercial FPGA toolflow and together provide mathematically strong protection against common bitstream attacks. Further, we quantify the difficulty of a removal attack on the protection circuitry through pattern matching and direct bitstream manipulation. The average area, power, and delay overhead for obfuscation with 95% mismatch probability are 18%, 16%, and 8%, respectively, for small combinational circuits, and 1%, 2%, and 5% for larger arithmetic modules.","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"73 1","pages":"1 - 22"},"PeriodicalIF":0.0,"publicationDate":"2020-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80455378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

A Theoretical Foundation for Timing Synchronous Systems Using Asynchronous Structures 采用异步结构的定时同步系统的理论基础

ACM Transactions on Design Automation of Electronic Systems (TODAES) Pub Date : 2020-02-03 DOI: 10.1145/3373355

R. Tadros, P. Beerel

引用次数: 2