Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory System

Arijit Nath, Sukarn Agarwal, H. Kapoor
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引用次数: 4

Abstract

Hybrid main memories comprising DRAM and Non-volatile memories (NVM) are projected as potential replacements of the traditional DRAM-based memories. However, traditional cache management policies designed for improving the hit rate lack awareness of the comparative latency of read-write for NVM blocks where the write latency is more than the read latency. Therefore, developing cache management techniques that reduce costly write-backs of the NVM blocks, yet maintain a fair hit rate in the cache, is of paramount importance. We propose two techniques based on the use of a small victim cache associated with the last-level cache that helps in retaining on the chip critical DRAM and NVM blocks. Victim cache being a scarce resource, we intend to keep only performance-critical blocks in the victim cache by exploiting the idea of reuse distance. The first technique, Victim Cache Replacement Policy, works on the replacement policy of the victim cache by preferential eviction of DRAM blocks over NVM blocks. However, the second technique, Prioritized Partitioning of victim cache, logically partitions the victim cache, giving a smaller share to the DRAM blocks and a relatively larger share to the NVM blocks. Experimental evaluation on full-system simulator shows significant improvement in system performance and reduction in the number of write-backs to the NVM partition of the main memory compared to the baseline and existing technique. Additionally, NVM reads and DRAM miss rate are also improved, leading to further performance enhancement.
基于重用距离的受害者缓存以有效利用混合主存系统
由DRAM和非易失性存储器(NVM)组成的混合主存储器被预测为传统的基于DRAM的存储器的潜在替代品。然而,为提高命中率而设计的传统缓存管理策略缺乏对NVM块的读写相对延迟的认识,其中写延迟大于读延迟。因此,开发既能减少代价高昂的NVM块回写,又能在缓存中保持合理命中率的缓存管理技术是至关重要的。我们提出了两种基于使用与最后一级缓存相关的小型受害者缓存的技术,该缓存有助于在芯片上保留关键的DRAM和NVM块。受害者缓存是一种稀缺资源,我们打算利用重用距离的思想,只在受害者缓存中保留性能关键的块。第一种技术,受害者缓存替换策略,通过优先删除DRAM块而不是NVM块来处理受害者缓存的替换策略。然而,第二种技术,即受害者缓存的优先分区,在逻辑上对受害者缓存进行分区,给DRAM块提供较小的份额,给NVM块提供相对较大的份额。在全系统模拟器上的实验评估表明,与基线和现有技术相比,系统性能有了显著提高,并且减少了对主内存NVM分区的回写次数。此外,NVM读取和DRAM丢失率也得到了改善,从而进一步提高了性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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