2022 IEEE International Solid- State Circuits Conference (ISSCC)最新文献

{"title":"A 0.049mm2 7.1-to-16.8GHz Dual-Core Triple-Mode VCO Achieving 200dB $mathbf{FoM}_{mathbf{A}}$ in 22nm FinFET","authors":"Jiang Gong, B. Patra, Luc Enthoven, J. V. Staveren, F. Sebastiano, M. Babaie","doi":"10.1109/ISSCC42614.2022.9731752","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731752","url":null,"abstract":"LC VCOs with low phase noise (PN) and an octave frequency-tuning range (FTR) are required for multistandard communication devices, software-defined radios, and wireline data links. A viable popular approach is to exploit multicore mode-switching VCOs for two reasons: (1) their PN improves linearly by in-phase coupling of N identical VCOs; (2) the resonant-mode switching enhances the VCO FTR without degrading the tank quality factor (Q) as no RF current ideally flows through lossy mode-selection switches. However, it is still challenging for dual-mode VCOs to achieve a competitive FoM while covering an octave FTR at oscillation frequencies $(mathrm{F}_{text{OSC}})$ above 6GHz [1]. To enhance the number of oscillation modes to 3, [2] added a center-loop inductor $(mathrm{L}_{mathrm{C}})$ to a transformer, as shown in Fig. 9.2.1. However, a large FTR gap is measured, since the transformer windings should be strongly coupled to accommodate $mathrm{L}_{mathrm{C}}$, The authors of [3] and [4] realized a triple- and quad-mode operation, respectively, by coupling two individual transformer-based resonators (see Fig. 9.2.1). Apart from the large area penalty, the former needs an extra third winding $(mathrm{L}_{mathrm{T}})$ in each transformer that degrades the tank Q, while the latter used large, fixed coupling capacitors $(mathrm{C}_{mathrm{M}})$ that load the tank in two of the resonant modes, thus limiting the VCO FTR.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"23 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91228414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ISSCC 2022 International Technical Program Committee","authors":"","doi":"10.1109/isscc42614.2022.9731741","DOIUrl":"https://doi.org/10.1109/isscc42614.2022.9731741","url":null,"abstract":"","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"24 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73441345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 100MHz-Reference, 8GHz/16GHz, 177fsrms/223fsrms RO-Based IL-ADPLL Incorporating Reference Octupler with Probability-Based Fast Phase-Error Calibration","authors":"Hyojun Kim, H. Oh, W. Jung, Yoonho Song, Jonghyun Oh, D. Jeong","doi":"10.1109/ISSCC42614.2022.9731714","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731714","url":null,"abstract":"A ring oscillator (RO) generates a multi-phase clock with a large tuning range in a small area, enabling a per-lane implementation in multilane communication applications. However, a high-frequency RO suffers from inferior phase noise, which is exacerbated by its high flicker-noise corner [1], being unsuitable to be a precision-timing clock source for a high-throughput interface. While injection locking widens the noise-suppression bandwidth of an RO-based phase-locked loop (PLL) [2], its effectiveness to overall jitter is limited only to those with low multiplication factors. By exploiting the accumulation-free nature of jitter in delay-locked loops [3], the reference multiplier in [4] generates a clean mid-frequency clock and then is cascaded to a high-frequency PLL, achieving a low output jitter despite a high multiplication factor. However, the background calibration for the large delay errors in the reference multiplier due to process, supply voltage, and temperature (PVT) variations necessitates an excessive settling time, which is in the order of a few milliseconds at worst. While the reference multiplier in [5] achieves very low noise, its calibration, which also requires a long settling time, should be preceded by a post-fabrication trimming. In [6], another viable method for reference multiplication is presented. However, the long calibration time remains unsolved due to the required low noise contribution of its calibration PLL. In this paper, we present a 100MHz-reference, 8GHz/16GHz RO-based injection-locked all-digital PLL (IL-ADPLL) that incorporates a reference octupler (8xREF) with a probability-based adaptive calibration algorithm. The presented algorithm enables a fast, accurate phase-error calibration both under startup and after sudden environmental disturbance, e.g., a supply hop.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"11 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88702841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface","authors":"Jonghak Yuh, Jason Li, Heguang Li, Y. Oyama, Cynthia Hsu, Pradeep Anantula, Stanley Jeong, Anirudh Amarnath, S. Darne, Sneha Bhatia, Tianyu Tang, Aditya Arya, Naman Rastogi, Naoki Ookuma, Hiroyuki Mizukoshi, Alex S. Yap, Demin Wang, Steve Kim, Yonggang Wu, Min Peng, Jason Lu, Tommy Ip, Seema Malhotra, David Han, Masatoshi Okumura, Jiwen Liu, J. Sohn, H. Chibvongodze, Muralikrishna Balaga, Aki Matsuda, Chakshu Puri, Chen Chen, I. V., C. G, Venky Ramachandra, Yosuke Kato, Ravi Kumar, Huijuan Wang, F. Moogat, In-Soo Yoon, K. Kanda, Takahiro Shimizu, N. Shibata, Takashi Shigeoka, K. Yanagidaira, T. Kodama, R. Fukuda, Yasuhiro Hirashima, Mitsuhiro Abe","doi":"10.1109/ISSCC42614.2022.9731110","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731110","url":null,"abstract":"The presented 1Tb 4b/cell 162 WL layer 3D Flash memory achieves an areal density of 15 Gb/mm2 which is 8.7% higher than prior work [1]. High-performance is the key enabler for 4b/cell NAND Flash to enter mainstream systems. This work delivers a 60MB/s programming throughput and a 65μs tR with an 8kB central WL stair architecture and contact-through-WL (CTW) region. 2.4Gb/s I/O speed is achieved with LTT and CTT combo drivers. A 45% reduction in the read and write data transfer energy is achieved by employing VCCQ domain design. A time-division peak-power-management (TD-PPM) feature effectively reduces system peak power while maximizing system performance. Cache DFT and I/O DFT functions enable a high-speed testing methodology at wafer level. These features are summarized and compared to previously reported 4b/cell Flash memories in Fig. 7.1.1.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"119 1","pages":"130-132"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88982474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 10GS/s 8b 25fJ/c-s 2850um2 Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology","authors":"Juzheng Liu, Mohsen Hassanpourghadi, M. Chen","doi":"10.1109/ISSCC42614.2022.9731625","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731625","url":null,"abstract":"High-speed (>GS/s) medium-resolution ADCs are in high demand for wideband communication ICs. Meanwhile, the increasing cost in advanced technology nodes favors area-efficient ADC architectures. The traditional voltage-domain time-interleaved (TI) SAR ADC [1]–[2] is a popular choice for its superior power efficiency. However, its single-channel sample rate is generally limited to <1GS/s, necessitating a large number of TI channels in high-sample-rate scenarios. It inevitably increases implementation overhead, including capacitive loading to the input driver and total area consumption. Recently, time-domain ADCs [3]–[5] have shown promising sampling speed, but are mostly based on thermometer coded time-to-digital converters (TDC). Unfortunately, the circuit complexity for such Flash TDC grows exponentially with the target bit resolution. Existing SAR TDCs [6] demonstrate a lower complexity but are generally limited in sample rate (MS/s). In this work, we propose a two-step time-domain ADC that uses a first-stage Flash TDC with the residue time quantized by the second-stage SAR TDC, targeting the >GS/s regime. To further improve the throughput of SAR TDC conversion, we propose a delay-tracking pipelining technique that allows the SAR TDC to quantize two residue time samples, simultaneously. At the circuit level, we use a selective delay tuning (SDT) cell to provide the time reference required for SAR conversion without using an excessive number of delay stages. A proof-of-concept ADC prototype in 14nm CMOS technology with 2x time interleaving achieves 10GS/s with 37.2dB SNDR at Nyquist frequency. It measures an energy efficiency of 24.8fJ/conv-step and occupies an active area of 2850um2, which are the highest reported energy efficiency and smallest area consumption among the state-of-the-art ADCs with> 10GS/s [7].","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"73 1","pages":"160-162"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90521068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator","authors":"Suneui Park, Seyeon Yoo, Yuhwan Shin, Jeonghyun Lee, Jaehyouk Choi","doi":"10.1109/ISSCC42614.2022.9731713","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731713","url":null,"abstract":"To generate low-jitter, high-frequency signals with ring oscillators (ROs), injection-locked clock multipliers (ILCMs) are the most suitable architecture due to advantages such wide bandwidth and fewer noise sources. However, they have two inherent issues. The first is that their jitter performance is sensitive to PVT variations. To address this problem, recent RO-ILCMs have been equipped with a multi-purpose, real-time digital calibrator that can remove both the frequency error of the RO and the phase error of the calibrator [1]–[2]. The second is that their operational stability and jitter performance degrade rapidly as the multiplication factor, N, increases. This issue, which has yet to be well addressed, is rooted in the fundamental limitation of the typical injection-locking method, i.e., injecting narrow pulses into the RO (top left of Fig. 13.2.1). When the free-running frequency of the RO deviates from the target frequency, $Nf_{text{REF}}$, where $f_{text{REF}}$ is the frequency of the reference clock $(mathcal{S}_{text{REF}})$, the core current of the RO $(I_{text{osc}})$ and the $text{injecting}$ current $(I_{text{INJ}})$ should be out of phase to satisfy the oscillation condition by creating the necessary phase shift. Thus, the effective magnitude of $I_{text{INJ}}$ at $N f_{text {REF, }} text {i.e}., I_{text{INJ,eff }}$, relative to $l_{text{osc}}$ determines the maximum phase angle, $phi_{text{MAX}}$, and, thus, the maximum lock range, $omega_{mathrm{L},text{MAX}}$ [3]. However, for a large $N, I_{text{INJ,eff} }$ becomes extremely small, sharply reducing $phi_{text{MAX}}$ and $omega_{mathrm{L},text{MAX}}$. Although the RO-ILCMs in [4]–[5] achieved a total $N$ of over 40 by using a reference doubler or quadrupler, their two-stage operation offers limited improvement of the jitter $text{FoM}$. MDLL-based implementations are better suited for larger N, but the time required for edge switching limits the maximum output frequency, $f_{text{OUT}}$, and the value of N.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"36 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90585256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Self-powering Wireless Soil-pH and Electrical Conductance Monitoring IC with Hybrid Microbial Electrochemical and Photovoltaic Energy Harvesting","authors":"Chuan-Yi Wu, Chi-Wei Liu, Jing-Siang Chen, Cong-Sheng Huang, Ting-Heng Lu, Ling-Chia Chen, I. Ou, Sook-Kuan Lee, Yen-Chi Chen, Po-Hung Chen, Chi-Te Liu, Ying-Chih Liao, Y. Liao","doi":"10.1109/ISSCC42614.2022.9731723","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731723","url":null,"abstract":"Soil monitoring provides comprehensive information on the ecosystem and soil functions, but it involves intensive field sampling and costly laboratory analysis. Advanced wireless sensor networks ease the sampling process and labor efforts [1]. However, the proliferation of wireless environmental monitoring applications is problematic in maintaining the power required for proper operation. Also, battery poses issues for minimizing sensor nodes and limiting environmental pollution. Ambient energy harvesting offers an alternative power supply to operate the sensor interface and wireless transceiver [2]–[5]. However, batteryless wireless sensor nodes typically suffer from low RF-powering sensitivity (~ -20dBm) [2], [5] and a short communication distance [4], making them unsuitable for wide-range environmental monitoring.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"9 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84234971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 1-to-18GHz Distributed-Stacked-Complementary Triple-Balanced Passive Mixer With up to 33dBm IIP3 and Integrated LO Driver in 45nm CMOS SOI","authors":"C. Hill, J. Buckwalter","doi":"10.1109/ISSCC42614.2022.9731662","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731662","url":null,"abstract":"Massive MIMO or digital-beamforming transceiver systems, shown in Fig. 19.7.1, offer flexibility for multiband, multi-user, and joint communication-and-sensing platforms. However, wideband MIMO applications increase the number of desired or interfering signals that impinge on each channel, creating higher input-power-compression $(mathrm{P}_{1text{dB}})$ or 3rd-order input-intercept-point (IIP3) linearity requirements in both the transmitting and receiving RF paths. In high-performance commercial and defense radios, CMOS mixers place critical limitations on receiver linearity as the LNA output typically compresses the mixer, leading to recent work on mixer-first approaches in CMOS to improve receiver linearity [1]. When highly linear microwave mixers are demanded, IIIV processes, such as GaAs, are favored for Schottky diodes, which offer lower $mathrm{R}_{text{on}}mathrm{C}_{text{off}}$ and high barrier voltages. Commercially available GaAs mixers offer IIP3s exceeding 30dBm. However, III-V mixers typically use a separate process for the driver amplifier, resulting in multiple chips with high driver power consumption (typically exceeding 1W) to deliver the required 15-to-30dBm LO power across a broad LO frequency range [2].","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"60 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87928547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SE2: Morning Session: Next Generation Circuit Designer 2022 Workshop","authors":"","doi":"10.1109/isscc42614.2022.9731553","DOIUrl":"https://doi.org/10.1109/isscc42614.2022.9731553","url":null,"abstract":"","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"25 1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88285817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 5V Input 98.4% Peak Efficiency Reconfigurable Capacitive-Sigma Converter With Greater than 90% Peak Efficiency for the Entire 0.4~1.2V Output Range","authors":"Xu Yang, Linhu Zhao, Menglian Zhao, Z. Tan, Lenian He, Yong Ding, Wuhua Li, W. Qu","doi":"10.1109/ISSCC42614.2022.9731550","DOIUrl":"https://doi.org/10.1109/ISSCC42614.2022.9731550","url":null,"abstract":"For the battery- or USB-powered portable smart devices, which supply their computing cores with a wide-range sub-volt rail, the energy-efficient high and wide voltage-conversion-ratio (VCR) converters are crucially important. In addition, low form factor and decent transient responses are also favorable for such applications. Prior state-of-the-art designs either use single-stage hybrid designs using multi-level or Dickson converters [1 – 3], or adopt two-stage cascaded architectures with a highly efficient unregulated front (or rear) stage [4], as shown in Fig. 18.6.1 (left). The multi-level designs, which conduct the full inductor current through all the on-state switches, are suited to low-to-medium power levels with limited current density. The Dickson converters take advantage of a high conversion ratio, however, at the cost of reduced output voltage range. The two-stage designs which show decent output range and efficiency, however, can suffer from heavy load efficiency degradation considering that the efficiency of both stages degrade with increasing load and the overall efficiency which is the product of the efficiencies of the two stages is severely degraded. Inspired by the inductive-sigma converter [5] which shunts a highly efficient unregulated LLC with a regulated Buck, this work proposes a reconfigurable capacitive-sigma converter. By input-series and output-shunting a highly efficient unregulated switched-capacitor (SC) converter with a reconfigurable Dickson hybrid Buck stage, the power stage input current is reused and output currents are combined. Therefore, the overall efficiency is greatly improved in a wide continuous VCR range and with an enhanced loading capacity. Besides, as will be demonstrated, the proposed design shows inherently decent load transient and regulation performances.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"41 1","pages":"108-110"},"PeriodicalIF":0.0,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88466802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}