A 480-Multiplication-Factor 13.2-to-17.3GHz Sub-Sampling PLL Achieving 6.6mW Power and -248.1 dB FoM Using a Proportionally Divided Charge Pump

Abstract

Beyond-10GHz frequency synthesizers are ubiquitous building blocks for today's ever-growing wireless and wireline communication systems. To meet the stringent requirements on data-rate and modulation schemes, the phase noise of the frequency synthesizers must be minimized. On the other hand, since low-noise and low-cost crystal oscillators operate in the MHz range, a > 10GHz frequency synthesizer demands a very large multiplication factor M (typically 400–1000), which poses new challenges. Although cascading PLLs helps reduce M per stage, it causes a significant power overhead and unwanted coupling between the two VCOs. Therefore, direct high M-factor frequency synthesis with low phase noise and low power consumption becomes a compelling approach.