A 25.8GHz Integer-N PLL With Time-Amplifying Phase-Frequency Detector Achieving 60fsrms Jitter, -252.8dB FoMJ, and Robust Lock Acquisition Performance

Abstract

With the rapid development of the modern communication technology, the communication standards impose stringent performance requirements, such as the ultra-low jitter requirement, on the phase-locked-loop (PLL) frequency synthesizers. As one of the widest-employed PLL structures, a charge-pump PLL (CPPLL) with a phase-frequency detector (PFD) is known for its excellent robust lock-acquisition performance due to the capability to detect phase and frequency error simultaneously. Recent research exhibited the great potential of the CPPLLs to achieve sub-100fsrms jitter [1]. However, a large current CP is adopted in [1] to minimize CP noise at the cost of high-power consumption. In this work, a 25.8GHz PLL with a time-amplifying phase-frequency detector (TAPFD) is implemented to suppress the CP noise by the high phase-error detection gain of the TAPFD and maintain the robust acquisition ability concurrently. The prototype is measured to achieve 60fsrms jitter and -252.8dB FoMJ.