70th Device Research Conference最新文献_第8页

Ultrafast spin torque memory based on magnetic tunnel junctions with combined in-plane and perpendicular polarizers 基于面内和垂直偏振片复合磁隧道结的超快自旋转矩记忆

70th Device Research Conference Pub Date : 2012-06-18 DOI: 10.1109/DRC.2012.6256944

I. Krivorotov, G. Rowlands, T. Rahman, J. Katine, J. Langer, A. Lyle, H. Zhao, J. G. Alzate, A. Kovalev, Y. Tserkovnyak, Z. Zeng, H. W. Jiang, K. Galatsis, Y. Huai, P. Amiri, K. Wang, J. Wang

{"title":"Ultrafast spin torque memory based on magnetic tunnel junctions with combined in-plane and perpendicular polarizers","authors":"I. Krivorotov, G. Rowlands, T. Rahman, J. Katine, J. Langer, A. Lyle, H. Zhao, J. G. Alzate, A. Kovalev, Y. Tserkovnyak, Z. Zeng, H. W. Jiang, K. Galatsis, Y. Huai, P. Amiri, K. Wang, J. Wang","doi":"10.1109/DRC.2012.6256944","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256944","url":null,"abstract":"Since the initial prediction and experimental demonstration of magnetization reversal by spin transfer torque (STT), there has been continuous progress toward the development of nonvolatile magnetic random access memory based on STT switching (STT-RAM) in nanoscale magnetic tunnel junctions (MTJs). In the most common STT-RAM configuration shown in Fig. 1(a), the magnetic moments of the free layer and the pinned polarizing layer of an MTJ lie collinear to one another in the plane of the junction. In this configuration (in-plane STT-RAM or IST-RAM), STT is small during the initial stages of the free layer's magnetic moment reversal, resulting in a relatively long nanosecond-scale switching time. Switching can be greatly accelerated in an alternative STT-RAM configuration, in which a second polarizer with magnetic moment perpendicular to the MTJ plane is added to the magnetic multilayer (orthogonal STT-RAM or OST-RAM). The initial STT from the perpendicular polarizer is large and has been predicted to induce ultrafast precessional switching of the free layer's magnetization on a time scale of 100 ps. The differences in the reversal modes expected for the IST-RAM and OST-RAM devices are illustrated in Figs. 1(c) and 1(d), wherein magnetization switching trajectories are shown for the two types of memory.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"1 1","pages":"211-212"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88924385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Epitaxial Si punch-through based selector for bipolar RRAM 基于外延Si穿孔的双极RRAM选择器

70th Device Research Conference Pub Date : 2012-06-18 DOI: 10.1109/DRC.2012.6256979

P. Bafna, P. Karkare, S. Srinivasan, S. Chopra, S. Lashkare, Y. Kim, S. Srinivasan, S. Kuppurao, S. Lodha, U. Ganguly

引用次数: 12

Electric field driven domain wall transfer in hybrid structures 杂化结构中电场驱动的畴壁转移

70th Device Research Conference Pub Date : 2012-06-18 DOI: 10.1109/DRC.2012.6256982

Xiaopeng Duan, V. Stephanovich, Y. Semenov, H. Fangohr, M. Franchin, K. W. Kim

引用次数: 0

Can quasi-saturation in the output characteristics of short-channel graphene field-effect transistors be engineered? 短沟道石墨烯场效应晶体管输出特性的准饱和可以被设计出来吗?

70th Device Research Conference Pub Date : 2012-06-18 DOI: 10.1109/DRC.2012.6256951

K. Ganapathi, M. Lundstrom, S. Salahuddin

引用次数: 1

Possible applications of topological insulator thin films for tunnel FETs 拓扑绝缘体薄膜在隧道场效应管中的可能应用

70th Device Research Conference Pub Date : 2012-06-18 DOI: 10.1109/DRC.2012.6256984

Jiwon Chang, L. Register, S. Banerjee

引用次数: 2

Will strong quantum confinement effect limit low VCC logic application of III–V FINFETs? 强量子约束效应是否会限制III-V型finfet的低VCC逻辑应用?

70th Device Research Conference Pub Date : 2012-06-18 DOI: 10.1109/DRC.2012.6256968

A. Nidhi, V. Saripalli, V. Narayanan, Y. Kimura, R. Arghavani, S. Datta

引用次数: 10

Electrical evidence of disorder at the SiO2/4H-SiC MOS interface and its effect on electron transport SiO2/4H-SiC MOS界面无序的电学证据及其对电子传递的影响

70th Device Research Conference Pub Date : 2012-06-18 DOI: 10.1109/DRC.2012.6257045

S. Swandono, A. Penumatcha, J. Cooper

引用次数: 2

Graphene field-effect transistors with self-aligned spin-on-doping of source/drain access regions 具有自对准自旋掺杂的石墨烯场效应晶体管

70th Device Research Conference Pub Date : 2012-06-18 DOI: 10.1109/DRC.2012.6256963

H. Movva, M. Ramón, C. Corbet, F. Chowdhury, G. Carpenter, E. Tutuc, S. Banerjee

{"title":"Graphene field-effect transistors with self-aligned spin-on-doping of source/drain access regions","authors":"H. Movva, M. Ramón, C. Corbet, F. Chowdhury, G. Carpenter, E. Tutuc, S. Banerjee","doi":"10.1109/DRC.2012.6256963","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256963","url":null,"abstract":"The exceptional electronic properties of graphene field-effect transistors (GFETs) make them a promlsmg replacement for conventional Si CMOS transistors for high frequency analog applications. Radio frequency GFETs with intrinsic cut-off frequencies as high as 300GHz have been reported, with theoretically predicted THz frequencies only being limited by fabrication challenges. A major factor responsible for degradation of GFET performance is high series resistance of the access regions between the source/drain contacts and the top-gated graphene channel, which reduces maximum possible drive currents. A back-gate bias can be used to modulate this resistance, but this approach does not provide for independent control of mUltiple GFETs on the same substrate and for GFETs on insulating substrates. GFETs with self-aligned gates overcome this problem by reducing the access region resistance, but their fabrication is not straightforward. Here, we propose a simple scheme of improving GFET performance by reducing the source/drain access resistance using self-aligned charge-transfer doping. A novel and controllable way of \"spin-on-doping\" of the access regions with chemical dopants is demonstrated.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"14 1","pages":"175-176"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89961236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Epitaxialy defined (ED) FinFET: to reduce VT variability and enable multiple VT 外延定义(ED) FinFET:减少VT变异性并实现多个VT

70th Device Research Conference Pub Date : 2012-06-18 DOI: 10.1109/DRC.2012.6256997

S. Mittal, S. Gupta, A. Nainani, M. Abraham, K. Schuegraf, S. Lodha, U. Ganguly

{"title":"Epitaxialy defined (ED) FinFET: to reduce VT variability and enable multiple VT","authors":"S. Mittal, S. Gupta, A. Nainani, M. Abraham, K. Schuegraf, S. Lodha, U. Ganguly","doi":"10.1109/DRC.2012.6256997","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256997","url":null,"abstract":"Device variability has become a major concern for CMOS technology [1]. Various sources of variability include Random Dopant Fluctuation (RDF), Gate Edge Roughness (GER) and Line Edge Roughness (LER) [2]. The introduction of FinFETs at 22nm node has two issues. Firstly, the effect of RDF is considerably reduced due to undoped fins [3]. But the aggressive fin width (Wfin) requirement (~Lg/3 [4]) to reduce short channel effect aggravates the electrical impact of LER and makes it greatest contributor to patterning induced variability [2]. Moreover, the edge roughness does not scale with technology and remains independent of the type of lithography used [5]. Secondly, multiple threshold voltage (VT) is achieved in planar technology by various patterned implant steps, which is unavailable for FinFET technology as the fin is undoped. Multiple VT transistor technology is essential for power vs. performance optimization by circuit designers [6]. In this work, we propose an alternative to conventional FinFET structure which can (a) reduce overall variability by 4× reduction in sensitivity to LER and (b) enable multiple VT by applying body bias dynamically without any costly patterned implant steps.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"10 1","pages":"127-128"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90991301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Bilayer graphene vertical tunneling field effect transistor 双层石墨烯垂直隧道场效应晶体管

70th Device Research Conference Pub Date : 2012-06-18 DOI: 10.1109/DRC.2012.6256932

D. Reddy, L. Register, S. Banerjee

{"title":"Bilayer graphene vertical tunneling field effect transistor","authors":"D. Reddy, L. Register, S. Banerjee","doi":"10.1109/DRC.2012.6256932","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256932","url":null,"abstract":"Electronic devices have been explored in the past based on resonant single-electron CB (conduction band) to CB tunneling between parallel quasi-two dimensional (2D) quantum wells within III-V heterostructures and their accompanying negative differential resistance (NDR) [1]. Such devices are attractive for high speed electronics, and digital logic circuits also have been demonstrated using a combination of conventional and such NDR FETs [2]. For two graphene layers separated by a tunnel barrier, we recently proposed the ultra-low-voltage Bilayer pseudoSpin FET (BiSFET) which would employ enhanced nonresonant VB (valence band) to CB tunneling, with a nevertheless very sharp NDR characteristic based on a predicted room-temperature many-body superfluid state [3]. However, NDR due to resonant single-particle CB-to-CB or VB-to-VB tunneling may also be achievable in such a structure. Furthermore, the atomically near-perfect 2D nature of the component graphene layers and the conduction/valence band symmetry may offer advantages over III-Vs. Here, we model the I-V characteristics due to single-particle tunneling in such a structure, Fig. 1, using a perturbative tunneling Hamiltonian approach [4,5], and deviations from this simple theory using atomistic tight-binding nonequilibrium Green's function (NEGF) simulation.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"23 1","pages":"73-74"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87275691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6