{"title":"Background LMS Calibration Algorithm Realization for SAR-ADC","authors":"Liu Wei, Guo Shangshang, W. Xiao, Shang Shiguang","doi":"10.1109/ICICM54364.2021.9660322","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660322","url":null,"abstract":"In order to minimize the impact of SAR-ADC capacitance weight mismatch on conversion accuracy, a digital calibration algorithm applied to SAR-ADC is implemented based on sub-binary technology and perturbation technology. A Subradix-2 SAR-ADC model was established with Simulink. The LMS adaptive calibration algorithm was used to calibrate the output iteratively, and the algorithm was implemented on FPGA Xilinx Spartan-6 device. The results show that when the input signal frequency is 239.19kHz and the sampling frequency is 1MS/s, the ENOB is increased from 9.57 bit to 11.78bit.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"178 1","pages":"142-146"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80680678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Hybrid FDTD-LUT Algorithm and Simulator for Electromagnetic Analyzing in Digital Integrated Circuits","authors":"Weifeng Liang, Huimin Liu, Tao Su","doi":"10.1109/ICICM54364.2021.9660361","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660361","url":null,"abstract":"In this paper, a hybrid simulation algorithm called FDTD-LUT, which bases on the finite difference time-domain (FDTD) algorithm and Look-up table (LUT) method, is proposed for analyzing the electromagnetic field of digital integrated circuits. Moreover, an electromagnetic field simulator Hybrid Electromagnetic Simulator for Integrated Circuit (HESIC) is developed by using this algorithm, which can be used for field circuit co-simulation of active-passive hybrid structure. The correctness of the algorithm is verified by comparing the simulation result of the H-tree clock distribution network (CDN) structure with the actual measured data of the H-tree CDN structure.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"9 1","pages":"23-27"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84291705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Research of Microprocessor Electrical Fast Transient Pulse Group Testing","authors":"Lei Liu, Wenxiao Fang, Xiangjun Lu, Shuwang Dai","doi":"10.1109/ICICM54364.2021.9660269","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660269","url":null,"abstract":"Electrical Fast Transient Pulse (EFT) is a kind of transient pulse interference caused by lightning, grounding fault or the switching of inductive load in circuit. Researchers from Cisco, Intel and other companies have proposed a model to simulate the EFT pulse coupling into the IC’s power pin and input/output (I/O) pin through the EFT transient disturbance rejection direction, which is used to study the EFT disturbance rejection capability of Microcontroller unit(MCU). However, there is no failure analysis for the failed pins. This article uses a device to conduct EFT interference experiment on MCU, and analyze the failure of the faulty pin. Experiment result shows that MCU failure occurs when the coupling voltage is about 10V, and the damage is about 30V.According to the analysis of the experimental results, during the EFT test process, the power supply pins start to fail when the coupling voltage is very small and the voltage when burning is also small, which has a great impact on the EFT performance of the entire MCU. Therefore, it is necessary to consider the protection of I/O pins and strictly design the EFT protection structure of MCU.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"99 1","pages":"85-89"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81468863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Z. Tang, Fangxu Lv, Jianjun Shi, Jinwang Zhang, Zheng Wang, Peng Li
{"title":"112Gbps High-speed SerDes Transmitter Based on Duo-Binary Pam4 Encoding","authors":"Z. Tang, Fangxu Lv, Jianjun Shi, Jinwang Zhang, Zheng Wang, Peng Li","doi":"10.1109/ICICM54364.2021.9660352","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660352","url":null,"abstract":"A 112Gb/s SerDes transmitter has been designed using Duo-binary PAM4 coding technology to effectively deal with the problem of high BER in serial transceivers under strong channel time. Using Duo-binary PAM4 coding technology, the problem of excessive fading of high speed PAM4 (Pulse Amplitude Modulation-4) signals under strong channels has been solved. The transmitter is powered by a CMOS 28nm process at 0.9V. Simulation results show that the transmitter can operate at 112Gb/s with 20.9dB channel attenuation, a supply voltage of 0.9V, a DC power consumption of 212.8mW, an energy efficiency of 1.9pJ/bit, and a sexiness of 88.3%.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"2021 1","pages":"73-76"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74298612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Qian Qi, Ming Wang, Yanhui Yang, Hongfei Hu, Yu-feng Guo, Xiaopeng Li, Youtao Zhang, Yi Zhang
{"title":"A 12-bit 4GS/s DAC based on CMOS/InP heterogeneous integration","authors":"Qian Qi, Ming Wang, Yanhui Yang, Hongfei Hu, Yu-feng Guo, Xiaopeng Li, Youtao Zhang, Yi Zhang","doi":"10.1109/ICICM54364.2021.9660318","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660318","url":null,"abstract":"This paper presents a 12-bit 4GS/s DAC in heterogeneous integration process of SMIC 0.18 $mu$ m CMOS and 0.7 $mu$ m InP HBT technology. The digital circuit is fabricated in CMOS technology to achieve high integration and low power consumption, while the analog circuit is composed by InP HBT technology with great high frequency performance. In this paper, a current-source switch structure is designed to reduce the variance of output impedance between ON and OFF states. Meanwhile, a deglitch circuit based on InP technology is added after the output of DAC to improve high frequency performance. The SFDR of the DAC at Nyquist-rate can reach more than 65dB.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"19 817 1","pages":"201-204"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85579504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dynamic Anchors Mechanism for Data Collection Using Mobile Sink in Wireless Sensor Networks","authors":"Shi-Yong Chen","doi":"10.1109/ICICM54364.2021.9660221","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660221","url":null,"abstract":"Using the mobile sink for data collection from all sensors is the most highly effective way to prolong the network lifetime of wireless sensor networks(WSNs). Many studies focused on the anchors selection, aiming to reduce the path length of mobile sink and prolong the network lifetime. However, the appropriateness and the number of the selected anchors, which significantly impact the network lifetime of the entire WSNs, still can be improved. This paper proposes a Dynamic Anchor Points Mechanism for data collection, called DAM, aiming to select appropriate anchors under the path length constraint for prolonging the network lifetime. The experimental results show that the proposed DAM outperforms existing data collection mechanisms in term of network lifetime and fairness index.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"129 1","pages":"337-341"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85759875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of a Software-Defined Transceiver with High Flexibility for Sensing Applications","authors":"Wei Song, Yusong Wu, Heng Huang, Milin Zhang","doi":"10.1109/ICICM54364.2021.9660248","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660248","url":null,"abstract":"This paper proposed a design of software-defined transceiver: A low-power digital baseband processor (DBP) was designed and fabricated in $40 nm$ CMOS process. The modulator and channel coding parameters of the DBP can be re-configured while the proposed design is used in different scenarios. A design flow of software-defined transceivers based on a COTS (Commercial Off-the-Shelf) radio platform was proposed. A programmable transceiver paired with the DBP was proposed and implemented on this platform, enabling the ability to interface with different higher layer protocols. Simulation results show that the DBP consumes $92.8 mu W$ power in a work load of 840 kbps, and the programmable transceiver can achieve a bit error rate of $10^{-4}$ at the signal to noise ratio of 15 dB. The proposed transceiver has been verified in the bench test.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"27 1","pages":"323-327"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87316229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhili Lan, Renhua Liu, Xiaojin Li, Yabin Sun, Yanling Shi
{"title":"Thermal Transient Measurement and Dimension-dependent Modeling of Self-heated Advanced Devices","authors":"Zhili Lan, Renhua Liu, Xiaojin Li, Yabin Sun, Yanling Shi","doi":"10.1109/ICICM54364.2021.9660292","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660292","url":null,"abstract":"In the era of 3D device, the self-heating effect brings higher temperature to device, and significantly affects the electrical performance of device. Accurate thermal modeling is required to optimize the device structure and circuit design. In this paper, a fifth-order thermal RC network is developed to describe the transient heating process based on the transient thermal simulation of 14-nm FinFET technology. Moreover, a size-dependent dynamic thermal model including fin width, fin height, extension length and materials of the source and drain extension regions, and the thickness of the shallow trench isolation (STI) is developed to estimate the peak temperature at given frequency. The parameters are randomly selected to verify the proposed models, and the average mean relative error of the dimension-dependent model is about 0.42 %, the root mean square error is about 2.33 K.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"32 1","pages":"305-308"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81100133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yue Bing, Zhao Lin, Lin Haofan, Zhou Luyao, Yang Zhi, Liu Shuang
{"title":"Analysis of 500kV Capacitive Voltage Transformer Leakage Fault","authors":"Yue Bing, Zhao Lin, Lin Haofan, Zhou Luyao, Yang Zhi, Liu Shuang","doi":"10.1109/ICICM54364.2021.9660338","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660338","url":null,"abstract":"Capacitive voltage transformers are increasingly used in power grids. Abnormal failures and other situations have also increased. In-depth analysis of the failure mechanism of CVT is conducive to improving the monitoring technology and means, intervening in advance to reduce the occurrence of serious accidents. This article focuses on the analysis of the cause of the oil leakage failure CVT and the disassembly inspection of the return to the factory to find out the cause of the failure and provide theoretical support for the subsequent avoidance of the same type of failure.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"403-407"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86972102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low-Offset CMOS Analog Amplitude Calculation Circuit in Hall Angle Sensor","authors":"B. Yuan, Langqi Xiao, Jing Ying, Bingyuan Wang","doi":"10.1109/ICICM54364.2021.9660323","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660323","url":null,"abstract":"Considering the hall angle sensor applications, a novel amplitude calculation circuit for sine and cosine signals is presented. It is consisted by double sampling and holding circuit, squaring circuit and summing circuit. By utilizing same MOSFETs rather than the traditional current mirror structure in the double sampling and holding circuit, the influence of the input offset voltage of the amplifier is eliminated. The proposed squaring and summing circuits eliminate the angular information to obtain the square of the amplitude of the sine and cosine signals. Spectre simulation results show that the squaring circuit works well in a 0.18 um CMOS process with 1.2 % output linearity error. The Monte Carlo simulation shows that the standard deviation of output is only 3.19 mV.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"27 1","pages":"36-39"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81418550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}