发布求助
文献互助 智能选刊 最新文献

2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)最新文献

筛选
英文 中文
High-modulus Current-reused Injection-Locked Frequency Dividers (FDs) with an Odd-modulus Sub-FD 具有奇模数Sub-FD的高模量电流复用注入锁定分频器(FDs)
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660255
S. Jang, W. Lai, M. Juang
{"title":"High-modulus Current-reused Injection-Locked Frequency Dividers (FDs) with an Odd-modulus Sub-FD","authors":"S. Jang, W. Lai, M. Juang","doi":"10.1109/ICICM54364.2021.9660255","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660255","url":null,"abstract":"This letter studies high-modulus LC injection-locked frequency dividers (ILFDs) designed with the current-reused technique, which uses two sub-circuits sharing the same dc current and device components. The current-reused ILFDs use one divide-by-3 ILFD and they include $div 6, div 9$ and $div 10$ ILFDs. These circuits cannot be obtained by cascading even-modulus ILFDs. Since the supply current to one sub-ILFD is limited by the other sub-ILFD, the design of a sub-circuit is different from the design of the voltage-mode ILFD. The current-reused $div 6$ ILFD was designed in the TSMC 0.18 $mu mathrm{m}$ BiCMOS process. It is based on a $div 2$ LC p-core ILFD stacking on a $div 3$ LC n-core capacitive cross-coupled ILFD. At the drain-source bias VDD of 1.6/1.2 V and at the incident power of 0dBm, the locking range is 3/2GHz (23.62/15.87%), from the incident frequency 11.2/11.6 GHz to 14.2/13.6 GHz. The core power consumption is 17. 47/6.312mW and the die area is $0.988 times 1.0185 mathrm{mm}^{2}$.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"357-361"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77083720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A K-band Diffential-output GaAs pHEMT Voltage Controlled Oscillator 一种k波段差分输出GaAs pHEMT压控振荡器
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660350
Hao Zhou
{"title":"A K-band Diffential-output GaAs pHEMT Voltage Controlled Oscillator","authors":"Hao Zhou","doi":"10.1109/ICICM54364.2021.9660350","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660350","url":null,"abstract":"In this paper, a K-band GaAs pHEMT voltage-controlled oscillator chip with differential-output is presented. The differential Colpitts Structure is adopted in this circuit design with two core oscillating loops integrated inside. Simulated results show this oscillator design can operates from 22.99GHz to 27.39GHz, with its relatively tuning frequency bandwidth of 17.47%. The single-ended output power of the chip is around 5dBm. A prototype chip is fabricated using PD25 process of Win foundry and is soldered on the test printed circuit board for performance measurement. The measurement results agree well with the simulated results. The prototype chip can operate from 23.24GHz to 28.17GHz, with its tuning voltage varied from -3V to 0V, achieving a relatively tuning bandwidth of 19.18%. The measured output power of the prototype is 4.5dBm with the differential-output single-ended. Phase noise performance is also provided, with the simulated and measured results agreed with each other well. Phase noise at 100KHz offset for the operating frequency band is around -80dBc/Hz.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"5 1","pages":"394-397"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81973124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low complexity Bang-Bang PD Design of 112Gb/s Duo-Binary PAM-4 CDR 112Gb/s双二进制PAM-4话单的低复杂度Bang-Bang PD设计
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660249
Jinwang Zhang, Fangxu Lv, Zhengbin Pang, Jianjun Shi, Zixiang Tang, Geng Zhang
{"title":"Low complexity Bang-Bang PD Design of 112Gb/s Duo-Binary PAM-4 CDR","authors":"Jinwang Zhang, Fangxu Lv, Zhengbin Pang, Jianjun Shi, Zixiang Tang, Geng Zhang","doi":"10.1109/ICICM54364.2021.9660249","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660249","url":null,"abstract":"The Bang-Bang phase detector (PD) design scheme of duo-binary(DB) four-level pulse amplitude modulation (PAM4) clock data recovery (CDR) with 112 Gb/s is put forward. In order to solve the problem of high signal attenuation and high bit error rate (BER) of high-speed serial transceiver, DB PAM-4 is used instead of PAM-4 technology to reduce signal loss. Aiming at the problem of complex phase detection of DB PAM-4 CDR based on multilevel modulation, a low complexity DB PAM-4 PD based on waveform filtering technique is proposed. The CDR model is constructed in Candence virtuoso with a working rate of 112 Gb/s. When the input jitter is 0. 5UI, the maximum jitter after locking is 1.2ps.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"2 1","pages":"351-356"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86878782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Reinforcement Learning-based Online-training AI Controller for DC-DC Switching Converters 基于强化学习的DC-DC开关变换器在线训练AI控制器
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660319
Xue Shi, Nan Chen, Ting-Yu Wei, Jiayu Wu, Peilei Xiao
{"title":"A Reinforcement Learning-based Online-training AI Controller for DC-DC Switching Converters","authors":"Xue Shi, Nan Chen, Ting-Yu Wei, Jiayu Wu, Peilei Xiao","doi":"10.1109/ICICM54364.2021.9660319","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660319","url":null,"abstract":"A controller for DC-DC switching converters based on solely AI algorithm is proposed with a simpler structure than the traditional neural network-PID controllers. Reinforcement learning is used to train the AI controller online using deep deterministic policy gradient (DDPG) algorithm. The AI controller with an actor-critical architecture realizes model-free control with strong self-adaptive ability for different control objects, which can be used for different types of DC-DC switching converters. The performance of a buck DC-DC switching converter with the AI controller is compared with a neural network-PID controller through simulation. The simulation results show that the settling time is improved by at least 65% and overshoot/undershoot is decreased by at least 43%.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"39 1","pages":"435-438"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73681658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
[ICICM 2021 Front cover] [ICICM 2021封面]
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/icicm54364.2021.9660296
{"title":"[ICICM 2021 Front cover]","authors":"","doi":"10.1109/icicm54364.2021.9660296","DOIUrl":"https://doi.org/10.1109/icicm54364.2021.9660296","url":null,"abstract":"","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"03 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72618285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Measurement Setup for Physical Unclonable Functions 物理不可克隆功能的测量装置
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660305
J. Biba, S. Boche, Nezar-Hekmat Sadek, W. Hansch
{"title":"Measurement Setup for Physical Unclonable Functions","authors":"J. Biba, S. Boche, Nezar-Hekmat Sadek, W. Hansch","doi":"10.1109/ICICM54364.2021.9660305","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660305","url":null,"abstract":"The use of physical unclonable functions (PUFs) to generate fingerprints for authentication of chips or larger electronic systems or for generation of internal cryptographic keys for data transfer is investigated. With the implementation of PUFs, each chip or electronic system has its own identity, which should prevent counterfeiting and “night shift” problems. There are various approaches to creating PUFs, and one of them is the so-called coating PUF, which would open the way to cost-effective and flexible protection during and after chip fabrication. In this work, we present two different capacitance measurement methods for fabricated PUF structures consisting of individual metal-oxide-semiconductor (MOS) capacitors. The goal is to obtain an easy and highly accurate measurement setup. Our fabricated PUF chips show an intended variation in capacitance and therefore generate characteristic fingerprints. We show that the parasitic capacitances and measurement variation are much smaller than the intended fluctuation of our PUF capacitances. This enables us to generate reliable and less error-prone fingerprints. Our presented measurement methods in combination with the technological PUF structures have shown to be accurate and reliable for flexible commercial application.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"35 1","pages":"155-159"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74499835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
112Gbps High-speed SerDes Transmitter Based on Duo-Binary Pam4 Encoding 基于双二进制Pam4编码的112Gbps高速串行发射机
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660352
Z. Tang, Fangxu Lv, Jianjun Shi, Jinwang Zhang, Zheng Wang, Peng Li
{"title":"112Gbps High-speed SerDes Transmitter Based on Duo-Binary Pam4 Encoding","authors":"Z. Tang, Fangxu Lv, Jianjun Shi, Jinwang Zhang, Zheng Wang, Peng Li","doi":"10.1109/ICICM54364.2021.9660352","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660352","url":null,"abstract":"A 112Gb/s SerDes transmitter has been designed using Duo-binary PAM4 coding technology to effectively deal with the problem of high BER in serial transceivers under strong channel time. Using Duo-binary PAM4 coding technology, the problem of excessive fading of high speed PAM4 (Pulse Amplitude Modulation-4) signals under strong channels has been solved. The transmitter is powered by a CMOS 28nm process at 0.9V. Simulation results show that the transmitter can operate at 112Gb/s with 20.9dB channel attenuation, a supply voltage of 0.9V, a DC power consumption of 212.8mW, an energy efficiency of 1.9pJ/bit, and a sexiness of 88.3%.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"2021 1","pages":"73-76"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74298612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 80.88-87.53GHz Millimeter Wave Wide Tuning Range Digitally Controlled Oscillator in 40nm CMOS 80.88-87.53GHz毫米波宽调谐范围的40nm CMOS数字控制振荡器
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660303
Yilu Chen, Lu Tang, Sicong Xia
{"title":"A 80.88-87.53GHz Millimeter Wave Wide Tuning Range Digitally Controlled Oscillator in 40nm CMOS","authors":"Yilu Chen, Lu Tang, Sicong Xia","doi":"10.1109/ICICM54364.2021.9660303","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660303","url":null,"abstract":"This article presents a millimeter wave high-resolution digitally controlled oscillator (DCO) in 40nm CMOS technology. The proposed oscillator achieves a frequency tuning accuracy of 2.6MHz by using switched capacitor array and on-chip transformer coupling technology. The tuning range is extended to $80.88 sim 87.53mathrm{GHz}$ by digital control artificial dielectric (DiCAD) technology. The phase noise of 80.88GHz at the frequency offset of lMHz and lOMHz is -93.23dBc/Hz and - 114.05dBc/Hz, and the core circuit layout area is $0.23times 0.13 mathrm{mm}2$. In addition, the peak-to-peak output amplitude of DCO is greater than 1V, which meets the crossover requirements of the post-stage injection-locked frequency divider.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"26 1","pages":"151-154"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90077960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a Software-Defined Transceiver with High Flexibility for Sensing Applications 一种具有高灵活性的软件定义收发器的设计
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660248
Wei Song, Yusong Wu, Heng Huang, Milin Zhang
{"title":"Design of a Software-Defined Transceiver with High Flexibility for Sensing Applications","authors":"Wei Song, Yusong Wu, Heng Huang, Milin Zhang","doi":"10.1109/ICICM54364.2021.9660248","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660248","url":null,"abstract":"This paper proposed a design of software-defined transceiver: A low-power digital baseband processor (DBP) was designed and fabricated in $40 nm$ CMOS process. The modulator and channel coding parameters of the DBP can be re-configured while the proposed design is used in different scenarios. A design flow of software-defined transceivers based on a COTS (Commercial Off-the-Shelf) radio platform was proposed. A programmable transceiver paired with the DBP was proposed and implemented on this platform, enabling the ability to interface with different higher layer protocols. Simulation results show that the DBP consumes $92.8 mu W$ power in a work load of 840 kbps, and the programmable transceiver can achieve a bit error rate of $10^{-4}$ at the signal to noise ratio of 15 dB. The proposed transceiver has been verified in the bench test.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"27 1","pages":"323-327"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87316229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of 500kV Capacitive Voltage Transformer Leakage Fault 500kV电容式电压互感器漏电故障分析
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660338
Yue Bing, Zhao Lin, Lin Haofan, Zhou Luyao, Yang Zhi, Liu Shuang
{"title":"Analysis of 500kV Capacitive Voltage Transformer Leakage Fault","authors":"Yue Bing, Zhao Lin, Lin Haofan, Zhou Luyao, Yang Zhi, Liu Shuang","doi":"10.1109/ICICM54364.2021.9660338","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660338","url":null,"abstract":"Capacitive voltage transformers are increasingly used in power grids. Abnormal failures and other situations have also increased. In-depth analysis of the failure mechanism of CVT is conducive to improving the monitoring technology and means, intervening in advance to reduce the occurrence of serious accidents. This article focuses on the analysis of the cause of the oil leakage failure CVT and the disassembly inspection of the return to the factory to find out the cause of the failure and provide theoretical support for the subsequent avoidance of the same type of failure.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"403-407"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86972102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书