Design of a Software-Defined Transceiver with High Flexibility for Sensing Applications

Abstract

This paper proposed a design of software-defined transceiver: A low-power digital baseband processor (DBP) was designed and fabricated in $40 nm$ CMOS process. The modulator and channel coding parameters of the DBP can be re-configured while the proposed design is used in different scenarios. A design flow of software-defined transceivers based on a COTS (Commercial Off-the-Shelf) radio platform was proposed. A programmable transceiver paired with the DBP was proposed and implemented on this platform, enabling the ability to interface with different higher layer protocols. Simulation results show that the DBP consumes $92.8 \mu W$ power in a work load of 840 kbps, and the programmable transceiver can achieve a bit error rate of $10^{-4}$ at the signal to noise ratio of 15 dB. The proposed transceiver has been verified in the bench test.