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2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)最新文献

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Thermal Transient Measurement and Dimension-dependent Modeling of Self-heated Advanced Devices 自加热先进器件的热瞬态测量与尺寸相关建模
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660292
Zhili Lan, Renhua Liu, Xiaojin Li, Yabin Sun, Yanling Shi
{"title":"Thermal Transient Measurement and Dimension-dependent Modeling of Self-heated Advanced Devices","authors":"Zhili Lan, Renhua Liu, Xiaojin Li, Yabin Sun, Yanling Shi","doi":"10.1109/ICICM54364.2021.9660292","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660292","url":null,"abstract":"In the era of 3D device, the self-heating effect brings higher temperature to device, and significantly affects the electrical performance of device. Accurate thermal modeling is required to optimize the device structure and circuit design. In this paper, a fifth-order thermal RC network is developed to describe the transient heating process based on the transient thermal simulation of 14-nm FinFET technology. Moreover, a size-dependent dynamic thermal model including fin width, fin height, extension length and materials of the source and drain extension regions, and the thickness of the shallow trench isolation (STI) is developed to estimate the peak temperature at given frequency. The parameters are randomly selected to verify the proposed models, and the average mean relative error of the dimension-dependent model is about 0.42 %, the root mean square error is about 2.33 K.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"32 1","pages":"305-308"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81100133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 12-bit 4GS/s DAC based on CMOS/InP heterogeneous integration 基于CMOS/InP异构集成的12位4GS/s DAC
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660318
Qian Qi, Ming Wang, Yanhui Yang, Hongfei Hu, Yu-feng Guo, Xiaopeng Li, Youtao Zhang, Yi Zhang
{"title":"A 12-bit 4GS/s DAC based on CMOS/InP heterogeneous integration","authors":"Qian Qi, Ming Wang, Yanhui Yang, Hongfei Hu, Yu-feng Guo, Xiaopeng Li, Youtao Zhang, Yi Zhang","doi":"10.1109/ICICM54364.2021.9660318","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660318","url":null,"abstract":"This paper presents a 12-bit 4GS/s DAC in heterogeneous integration process of SMIC 0.18 $mu$ m CMOS and 0.7 $mu$ m InP HBT technology. The digital circuit is fabricated in CMOS technology to achieve high integration and low power consumption, while the analog circuit is composed by InP HBT technology with great high frequency performance. In this paper, a current-source switch structure is designed to reduce the variance of output impedance between ON and OFF states. Meanwhile, a deglitch circuit based on InP technology is added after the output of DAC to improve high frequency performance. The SFDR of the DAC at Nyquist-rate can reach more than 65dB.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"19 817 1","pages":"201-204"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85579504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dynamic Anchors Mechanism for Data Collection Using Mobile Sink in Wireless Sensor Networks 无线传感器网络中移动Sink数据采集的动态锚点机制
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660221
Shi-Yong Chen
{"title":"Dynamic Anchors Mechanism for Data Collection Using Mobile Sink in Wireless Sensor Networks","authors":"Shi-Yong Chen","doi":"10.1109/ICICM54364.2021.9660221","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660221","url":null,"abstract":"Using the mobile sink for data collection from all sensors is the most highly effective way to prolong the network lifetime of wireless sensor networks(WSNs). Many studies focused on the anchors selection, aiming to reduce the path length of mobile sink and prolong the network lifetime. However, the appropriateness and the number of the selected anchors, which significantly impact the network lifetime of the entire WSNs, still can be improved. This paper proposes a Dynamic Anchor Points Mechanism for data collection, called DAM, aiming to select appropriate anchors under the path length constraint for prolonging the network lifetime. The experimental results show that the proposed DAM outperforms existing data collection mechanisms in term of network lifetime and fairness index.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"129 1","pages":"337-341"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85759875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-Offset CMOS Analog Amplitude Calculation Circuit in Hall Angle Sensor 霍尔角传感器中的低偏置CMOS模拟幅值计算电路
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660323
B. Yuan, Langqi Xiao, Jing Ying, Bingyuan Wang
{"title":"Low-Offset CMOS Analog Amplitude Calculation Circuit in Hall Angle Sensor","authors":"B. Yuan, Langqi Xiao, Jing Ying, Bingyuan Wang","doi":"10.1109/ICICM54364.2021.9660323","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660323","url":null,"abstract":"Considering the hall angle sensor applications, a novel amplitude calculation circuit for sine and cosine signals is presented. It is consisted by double sampling and holding circuit, squaring circuit and summing circuit. By utilizing same MOSFETs rather than the traditional current mirror structure in the double sampling and holding circuit, the influence of the input offset voltage of the amplifier is eliminated. The proposed squaring and summing circuits eliminate the angular information to obtain the square of the amplitude of the sine and cosine signals. Spectre simulation results show that the squaring circuit works well in a 0.18 um CMOS process with 1.2 % output linearity error. The Monte Carlo simulation shows that the standard deviation of output is only 3.19 mV.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"27 1","pages":"36-39"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81418550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of 500kV Capacitive Voltage Transformer Leakage Fault 500kV电容式电压互感器漏电故障分析
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660338
Yue Bing, Zhao Lin, Lin Haofan, Zhou Luyao, Yang Zhi, Liu Shuang
{"title":"Analysis of 500kV Capacitive Voltage Transformer Leakage Fault","authors":"Yue Bing, Zhao Lin, Lin Haofan, Zhou Luyao, Yang Zhi, Liu Shuang","doi":"10.1109/ICICM54364.2021.9660338","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660338","url":null,"abstract":"Capacitive voltage transformers are increasingly used in power grids. Abnormal failures and other situations have also increased. In-depth analysis of the failure mechanism of CVT is conducive to improving the monitoring technology and means, intervening in advance to reduce the occurrence of serious accidents. This article focuses on the analysis of the cause of the oil leakage failure CVT and the disassembly inspection of the return to the factory to find out the cause of the failure and provide theoretical support for the subsequent avoidance of the same type of failure.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"403-407"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86972102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
[ICICM 2021 Front cover] [ICICM 2021封面]
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/icicm54364.2021.9660296
{"title":"[ICICM 2021 Front cover]","authors":"","doi":"10.1109/icicm54364.2021.9660296","DOIUrl":"https://doi.org/10.1109/icicm54364.2021.9660296","url":null,"abstract":"","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"03 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72618285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Yolov3-tiny Object Detection SoC Based on FPGA Platform 基于FPGA平台的yolov3微型目标检测SoC
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660358
Hongbo Zhang, Jiaqi Jiang, Yunhao Fu, Yuchun Chang
{"title":"Yolov3-tiny Object Detection SoC Based on FPGA Platform","authors":"Hongbo Zhang, Jiaqi Jiang, Yunhao Fu, Yuchun Chang","doi":"10.1109/ICICM54364.2021.9660358","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660358","url":null,"abstract":"Object detection is a popular direction in computer vision and digital image processing and convolutional neural network have been widely used in this field. In the forward reasoning stage, many practical applications based on embedded platforms have stringent requirements for low latency and low power consumption. FPGA are undoubtedly the optimal solution to deal with such problems. Yolo [1] is one of the high-quality frameworks for object detection. Among them, Yolov3-tiny is a lightweight network that balances accuracy and network complexity. It is also the most popular object detection network in the industry. This article introduces the complete process of mapping the network structure to the FPGA based on the Yolov3tiny algorithm and optimizes the accelerator architecture for Zedboard to make it under limited resources to achieve the best performance. The experimental results show that the detection speed of 325.036ms/img and the performance of 24.32GOPS is obtained on Zedboard and the mAP of COCO is 32.6%. Compared with Xeon E5-2673 v4 CPU, the energy efficiency is 241times and the performance is 8 times; compared with single-core ARM-A9 CPU, its energy efficiency is 180.75 times and its performance is 402.12 times.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"4 1","pages":"291-294"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86376740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and UVM Verification of an RTC Subsystem with Temperature Compensation 带温度补偿的RTC子系统设计与UVM验证
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660348
Yuxin Liu, N. Tan, Xiaohui Xiao, Junhu Xia, Wanrong Hu, Yan Ding
{"title":"Design and UVM Verification of an RTC Subsystem with Temperature Compensation","authors":"Yuxin Liu, N. Tan, Xiaohui Xiao, Junhu Xia, Wanrong Hu, Yan Ding","doi":"10.1109/ICICM54364.2021.9660348","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660348","url":null,"abstract":"The real-time clock (RTC) integrated circuit is a special-purpose accurate clock generating circuit that is used in many microcontroller units (MCUs). In this paper, we design an ultra-low power and high-precision RTC subsystem used in general purpose MCUs. A temperature compensation scheme is designed to improve the accuracy of the RTC. The RTC uses a 1Hz clock for generating the accurate time and a 32768-Hz clock for the temperature compensation, which can reduce power consumption while maintaining high accuracy. To get the temperature from the analog-to-digital (ADC), we design an ADC controller. A power management unit (PMU) is designed to control the MCU to enter or exit the ultra-low power mode. We also build a subsystem-level verification environment for the RTC using the universal verification methodology (UVM) platform. The results show that the functions of the RTC under various conditions are correct and coverage reaches 98% in the regression test, the frequency error within the industrial temperature range is ± 1 ppm after calibration, and the accuracy meets the requirement of most MCUs.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"11 1","pages":"384-389"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90512566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 8KHz-Bandwidth 13.7bit-ENOB Low-Power Noise-Shaping SAR ADC Using Split-Capacitor DAC 采用分电容DAC的8khz带宽13.7位enob低功耗噪声整形SAR ADC
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660332
Jidong Zhou, Jihai Duan
{"title":"A 8KHz-Bandwidth 13.7bit-ENOB Low-Power Noise-Shaping SAR ADC Using Split-Capacitor DAC","authors":"Jidong Zhou, Jihai Duan","doi":"10.1109/ICICM54364.2021.9660332","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660332","url":null,"abstract":"This paper proposes a passive noise shaping successive approximation register (SAR) ADC based on split-capacitor DAC. The designed split-capacitor DAC helps to save chip area and power consumption. The designed noise shaping module helps to eliminate residual sampling. A passive gain of 6 can be achieved, and only a two-input dynamic comparator is used. The simulation results show that the ADC achieves 13.7-bit ENOB with 8 KHz signal bandwidth at the sampling rate of 400 KS/s in 180 nm CMOS technology, and the power consumption is only 7.65 uW.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"70 1","pages":"319-322"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73711664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 113.6 dB SNR 300μW Switched-Capacitor ΣΔ Modulator with Full-Scale Input Range 113.6 dB信噪比300μW全量程开关电容ΣΔ调制器
2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660342
Hehe Zhang, Cong Tang, Liang Zou, Yajie Qin
{"title":"A 113.6 dB SNR 300μW Switched-Capacitor ΣΔ Modulator with Full-Scale Input Range","authors":"Hehe Zhang, Cong Tang, Liang Zou, Yajie Qin","doi":"10.1109/ICICM54364.2021.9660342","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660342","url":null,"abstract":"A single-loop 3rd-order 1-bit switched-capacitor modulator in 180-nm CMOS technology is presented. A important feature of this modulator is the full-scale input signal range for high-precision and low-power application that is suitable for DC measurement. In order to achieve the full-scale input signal range, an effective signal-scaling circuit is added in the topology. The chopper stabilization technique is incorporated to calibrate the 1/f noise and DC offset. Meanwhile, the zero optimization technique is utilized in the feed-forward topology to optimize the SNR. To further improve the linearity of the modulator, the bootstrapped switches are used in sampling process. The designed modulator achieves 113.6 dB SNR over 250 Hz signal bandwidth with $pm V_{REF}$ differential input range, while drawing 110$mu$A current from a 2.7V supply and THD is below -100dB. The chip area is 1.76 mm2. This corresponds to FoM of 175.8dB.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"94 1","pages":"101-104"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73851970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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