2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)最新文献_第8页

Design and UVM Verification of an RTC Subsystem with Temperature Compensation 带温度补偿的RTC子系统设计与UVM验证

2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660348

Yuxin Liu, N. Tan, Xiaohui Xiao, Junhu Xia, Wanrong Hu, Yan Ding

{"title":"Design and UVM Verification of an RTC Subsystem with Temperature Compensation","authors":"Yuxin Liu, N. Tan, Xiaohui Xiao, Junhu Xia, Wanrong Hu, Yan Ding","doi":"10.1109/ICICM54364.2021.9660348","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660348","url":null,"abstract":"The real-time clock (RTC) integrated circuit is a special-purpose accurate clock generating circuit that is used in many microcontroller units (MCUs). In this paper, we design an ultra-low power and high-precision RTC subsystem used in general purpose MCUs. A temperature compensation scheme is designed to improve the accuracy of the RTC. The RTC uses a 1Hz clock for generating the accurate time and a 32768-Hz clock for the temperature compensation, which can reduce power consumption while maintaining high accuracy. To get the temperature from the analog-to-digital (ADC), we design an ADC controller. A power management unit (PMU) is designed to control the MCU to enter or exit the ultra-low power mode. We also build a subsystem-level verification environment for the RTC using the universal verification methodology (UVM) platform. The results show that the functions of the RTC under various conditions are correct and coverage reaches 98% in the regression test, the frequency error within the industrial temperature range is ± 1 ppm after calibration, and the accuracy meets the requirement of most MCUs.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"11 1","pages":"384-389"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90512566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Yolov3-tiny Object Detection SoC Based on FPGA Platform 基于FPGA平台的yolov3微型目标检测SoC

2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660358

Hongbo Zhang, Jiaqi Jiang, Yunhao Fu, Yuchun Chang

{"title":"Yolov3-tiny Object Detection SoC Based on FPGA Platform","authors":"Hongbo Zhang, Jiaqi Jiang, Yunhao Fu, Yuchun Chang","doi":"10.1109/ICICM54364.2021.9660358","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660358","url":null,"abstract":"Object detection is a popular direction in computer vision and digital image processing and convolutional neural network have been widely used in this field. In the forward reasoning stage, many practical applications based on embedded platforms have stringent requirements for low latency and low power consumption. FPGA are undoubtedly the optimal solution to deal with such problems. Yolo [1] is one of the high-quality frameworks for object detection. Among them, Yolov3-tiny is a lightweight network that balances accuracy and network complexity. It is also the most popular object detection network in the industry. This article introduces the complete process of mapping the network structure to the FPGA based on the Yolov3tiny algorithm and optimizes the accelerator architecture for Zedboard to make it under limited resources to achieve the best performance. The experimental results show that the detection speed of 325.036ms/img and the performance of 24.32GOPS is obtained on Zedboard and the mAP of COCO is 32.6%. Compared with Xeon E5-2673 v4 CPU, the energy efficiency is 241times and the performance is 8 times; compared with single-core ARM-A9 CPU, its energy efficiency is 180.75 times and its performance is 402.12 times.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"4 1","pages":"291-294"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86376740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A Wide Input Voltage Range, Low Quiescent Current LDO Using Combination Structure of Bandgap and Error Amplifier 采用带隙和误差放大器组合结构的宽输入电压范围、低静态电流LDO

2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660242

Yidong Cao, Zhiping Wen

{"title":"A Wide Input Voltage Range, Low Quiescent Current LDO Using Combination Structure of Bandgap and Error Amplifier","authors":"Yidong Cao, Zhiping Wen","doi":"10.1109/ICICM54364.2021.9660242","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660242","url":null,"abstract":"This paper presents a wide input voltage range, low quiescent current low-dropout voltage (LDO) regulator. Featuring the NPN transistors in the BGR circuit operate as the differential input pair of operational trans conductance amplifier (OTA). Current mirror with $beta$ helper structure and class AB output stage of OTA are introduced to improve the accuracy of entire circuit. The proposed LDO is simulated based on 400 nm BCD process. The simulation results shows that the proposed LDO regulator achieved 3.2$mu$A quiescent current with the fixed output voltage 3. 3V. The BGR output voltage has a 186ppm$/^{circ}$C temperature coefficient (TC) when temperature varies from - 55°C to 125°C. The proposed LDO has a line regulation of 11mV when input voltage varies from 4.3V to 24V and a load regulation of 12.8mV with load current range from 5$mu$A to 50mA. The STB(stability) analysis result shows that the circuit provides a gain over 55dB with a gain-bandwidth (GBW) above 5kHz, and a phase margin (PM) over 45 degree with a load capacitor equal to 1$mu$F for different load conditions.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"65 1","pages":"240-245"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79970427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

[ICICM 2021 Front cover] [ICICM 2021封面]

2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/icicm54364.2021.9660296

引用次数: 0

A Reinforcement Learning-based Online-training AI Controller for DC-DC Switching Converters 基于强化学习的DC-DC开关变换器在线训练AI控制器

2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660319

Xue Shi, Nan Chen, Ting-Yu Wei, Jiayu Wu, Peilei Xiao

引用次数: 2

Influence of Silicon Via Morphology on RF Performance of TSV 硅孔形貌对TSV射频性能的影响

2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660357

You Yuejuan, Liu Dexi, Liu Yawei, Shi Lei

引用次数: 0

Measurement Setup for Physical Unclonable Functions 物理不可克隆功能的测量装置

2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660305

J. Biba, S. Boche, Nezar-Hekmat Sadek, W. Hansch

{"title":"Measurement Setup for Physical Unclonable Functions","authors":"J. Biba, S. Boche, Nezar-Hekmat Sadek, W. Hansch","doi":"10.1109/ICICM54364.2021.9660305","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660305","url":null,"abstract":"The use of physical unclonable functions (PUFs) to generate fingerprints for authentication of chips or larger electronic systems or for generation of internal cryptographic keys for data transfer is investigated. With the implementation of PUFs, each chip or electronic system has its own identity, which should prevent counterfeiting and “night shift” problems. There are various approaches to creating PUFs, and one of them is the so-called coating PUF, which would open the way to cost-effective and flexible protection during and after chip fabrication. In this work, we present two different capacitance measurement methods for fabricated PUF structures consisting of individual metal-oxide-semiconductor (MOS) capacitors. The goal is to obtain an easy and highly accurate measurement setup. Our fabricated PUF chips show an intended variation in capacitance and therefore generate characteristic fingerprints. We show that the parasitic capacitances and measurement variation are much smaller than the intended fluctuation of our PUF capacitances. This enables us to generate reliable and less error-prone fingerprints. Our presented measurement methods in combination with the technological PUF structures have shown to be accurate and reliable for flexible commercial application.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"35 1","pages":"155-159"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74499835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 80.88-87.53GHz Millimeter Wave Wide Tuning Range Digitally Controlled Oscillator in 40nm CMOS 80.88-87.53GHz毫米波宽调谐范围的40nm CMOS数字控制振荡器

2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660303

Yilu Chen, Lu Tang, Sicong Xia

引用次数: 0

A Data Eye Width Improved and ODT PVT Tolerance Enhanced DDR4 SDRAM Using Fast Clock Gating and tADC Self-align 基于快速时钟门控和tdac自对准的DDR4 SDRAM数据眼宽改善和ODT PVT容差增强

2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660276

Hongguang Zhang, Zhiqiang Zhang, Yuanyuan Gong, Yanan Zhang, Jake Jung, Brian Lee, Edwin Kim, Kanyu Cao

引用次数: 0

Analysis of Abnormal Defects of High Resistance of 1000 kV UHV Transmission Line 1000kv特高压输电线路高阻异常缺陷分析

2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI: 10.1109/ICICM54364.2021.9660218

Yue Bing, Zhou Luyao, Yang Zhi, Zhao Lin, Lin Haofan, Yang Yong

引用次数: 0