A 8KHz-Bandwidth 13.7bit-ENOB Low-Power Noise-Shaping SAR ADC Using Split-Capacitor DAC

This paper proposes a passive noise shaping successive approximation register (SAR) ADC based on split-capacitor DAC. The designed split-capacitor DAC helps to save chip area and power consumption. The designed noise shaping module helps to eliminate residual sampling. A passive gain of 6 can be achieved, and only a two-input dynamic comparator is used. The simulation results show that the ADC achieves 13.7-bit ENOB with 8 KHz signal bandwidth at the sampling rate of 400 KS/s in 180 nm CMOS technology, and the power consumption is only 7.65 uW.