基于CMOS/InP异构集成的12位4GS/s DAC

2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI:10.1109/ICICM54364.2021.9660318

Qian Qi, Ming Wang, Yanhui Yang, Hongfei Hu, Yu-feng Guo, Xiaopeng Li, Youtao Zhang, Yi Zhang

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引用次数: 0

摘要

本文提出了一种采用中芯国际0.18 $\mu$ m CMOS和0.7 $\mu$ m InP HBT技术异构集成工艺的12位4GS/s DAC。数字电路采用CMOS技术制作，实现了高集成度和低功耗，模拟电路采用InP HBT技术制作，具有很高的高频性能。本文设计了一种电流源开关结构，以减小输出阻抗在ON和OFF状态之间的变化。同时，在DAC输出后增加了基于InP技术的去glitch电路，提高了高频性能。在奈奎斯特速率下，DAC的SFDR可以达到65dB以上。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 12-bit 4GS/s DAC based on CMOS/InP heterogeneous integration

This paper presents a 12-bit 4GS/s DAC in heterogeneous integration process of SMIC 0.18 $\mu$ m CMOS and 0.7 $\mu$ m InP HBT technology. The digital circuit is fabricated in CMOS technology to achieve high integration and low power consumption, while the analog circuit is composed by InP HBT technology with great high frequency performance. In this paper, a current-source switch structure is designed to reduce the variance of output impedance between ON and OFF states. Meanwhile, a deglitch circuit based on InP technology is added after the output of DAC to improve high frequency performance. The SFDR of the DAC at Nyquist-rate can reach more than 65dB.

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2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)

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