Research of Microprocessor Electrical Fast Transient Pulse Group Testing

Lei Liu, Wenxiao Fang, Xiangjun Lu, Shuwang Dai
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Abstract

Electrical Fast Transient Pulse (EFT) is a kind of transient pulse interference caused by lightning, grounding fault or the switching of inductive load in circuit. Researchers from Cisco, Intel and other companies have proposed a model to simulate the EFT pulse coupling into the IC’s power pin and input/output (I/O) pin through the EFT transient disturbance rejection direction, which is used to study the EFT disturbance rejection capability of Microcontroller unit(MCU). However, there is no failure analysis for the failed pins. This article uses a device to conduct EFT interference experiment on MCU, and analyze the failure of the faulty pin. Experiment result shows that MCU failure occurs when the coupling voltage is about 10V, and the damage is about 30V.According to the analysis of the experimental results, during the EFT test process, the power supply pins start to fail when the coupling voltage is very small and the voltage when burning is also small, which has a great impact on the EFT performance of the entire MCU. Therefore, it is necessary to consider the protection of I/O pins and strictly design the EFT protection structure of MCU.
微处理器电快速瞬态脉冲群测试研究
快速瞬态脉冲是由雷电、接地故障或电路中感性负载的切换引起的一种瞬态脉冲干扰。Cisco、Intel等公司的研究人员提出了一个模型,通过EFT瞬态抗扰方向模拟EFT脉冲耦合到IC的电源引脚和输入/输出(I/O)引脚,用于研究微控制器(MCU)的EFT抗扰能力。然而,没有对失效引脚进行失效分析。本文利用装置在单片机上进行了EFT干扰实验,并对故障引脚的失效进行了分析。实验结果表明,当耦合电压约为10V时,单片机发生故障,损坏约为30V。根据实验结果分析,在EFT测试过程中,在耦合电压很小、燃烧电压也很小的情况下,电源引脚开始失效,这对整个MCU的EFT性能有很大的影响。因此,有必要考虑对I/O引脚的保护,严格设计单片机的EFT保护结构。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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