2018 IEEE Symposium on VLSI Technology最新文献

A Circuit Compatible Accurate Compact Model for Ferroelectric-FETs 一种电路兼容的精确紧凑铁电场效应管模型

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-18 DOI: 10.1109/VLSIT.2018.8510622

K. Ni, M. Jerry, Jeffrey A. Smith, S. Datta

引用次数: 101

Low RA Magnetic Tunnel Junction Arrays in Conjunction with Low Switching Current and High Breakdown Voltage for STT-MRAM at 10 nm and Beyond 10nm及以上STT-MRAM的低RA磁隧道结阵列与低开关电流和高击穿电压相结合

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-18 DOI: 10.1109/VLSIT.2018.8510653

C. Park, H. Lee, C. Ching, J. Ahn, R. Wang, M. Pakala, S. H. Kang

引用次数: 14

A Threshold Switch Augmented Hybrid-FeFET (H-FeFET) with Enhanced Read Distinguishability and Reduced Programming Voltage for Non-Volatile Memory Applications 一种用于非易失性存储器的阈值开关增强混合ffet (h - ffet)，具有增强的读可分辨性和降低的编程电压

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-18 DOI: 10.1109/VLSIT.2018.8510679

M. Jerry, A. Aziz, K. Ni, S. Datta, S. Gupta, N. Shukla

{"title":"A Threshold Switch Augmented Hybrid-FeFET (H-FeFET) with Enhanced Read Distinguishability and Reduced Programming Voltage for Non-Volatile Memory Applications","authors":"M. Jerry, A. Aziz, K. Ni, S. Datta, S. Gupta, N. Shukla","doi":"10.1109/VLSIT.2018.8510679","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510679","url":null,"abstract":"In this work, we demonstrate a novel Hybrid-FeFET (H-FeFET) that leverages the threshold switching characteristics of Ag/HfO<inf>2</inf> to overcome the fundamental trade-off between memory window MW /read current ratio (I<inf>read,1</inf>/I<inf>read,0</inf>) , and program voltage (V<inf>prog</inf>)/maximum electric-field in standard FeFETs for non-volatile memory application. The H-FeFET incorporates the threshold switch (TS) in the source of the FeFET, and is designed to exhibit a ferroelectric state-dependent volatile HRS to LRS transition (I<inf>ON</inf>/I<inf>OFF</inf> >107) – during read, the TS turns ON only if the FeFET is in the low-V<inf>T</inf> SET state, and remains OFF if the FeFET is in the high-V<inf>T</inf> RESET state, thus, selectively suppressing the RESET read current. Leveraging this principle, the H-FeFET: a Demonstrates 77% higher MW and 1000× larger I<inf>read,1</inf>/I<inf>read,0</inf> compared to the FeFET, at iso-V<inf>prog</inf> (DC); (b) Enables 25% reduction in V<inf>prog</inf> at iso-I<inf>read,1</inf>/I<inf>read,0</inf> during pulse operation-facilitated by the 8× improvement in I<inf>read,1</inf>/I<inf>read,0</inf>; (c) Exhibits 2.5×reduction in programming power at iso-I<inf>read,1</inf>/I<inf>read,0</inf> in the H-FeFET-based AND array architecture, as shown by simulations. Thus, the H-FeFET overcomes the FeFET design challenges while retaining its existing advantages, making it a promising candidate for nonvolatile memory applications.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"24 1","pages":"129-130"},"PeriodicalIF":0.0,"publicationDate":"2018-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89894588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Hole mobility enhancement in extremely-thin-body strained GOI and SGOI pMOSFETs by improved Ge condensation method 改进Ge凝聚法增强极薄体应变GOI和SGOI pmosfet的空穴迁移率

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510646

K. Jo, W. Kim, M. Takenaka, S. Takagi

引用次数: 3

A 12nm FinFET Technology Featuring 2nd Generation FinFET for Low Power and High Performance Applications 具有低功耗和高性能应用的第二代FinFET的12nm FinFET技术

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510632

H. Lo, D. Choi, Y. Hu, Y. Shen, Y. Qi, J. Peng, D. Zhou, M. Mohan, C. Yong, H. Zhan, H. Wei, X. He, D. Kang, A. Sirman, Y. Wang, H. Zang, S. Mun, A. Vinslava, W.H. Chen, C. Gaire, J. Liu, X. Dou, Y. Shi, P. Zhao, B. Zhu, A. Jha, X. Zhang, X. Wan, E. Lavigne, C. Kyono, M. Togo, J. Versaggi, H. Yu, O. Hu, J. lee, S. Samavedam, D. K. Sohn

引用次数: 4

Ferroelectric Switching Delay as Cause of Negative Capacitance and the Implications to NCFETs 导致负电容的铁电开关延迟及其对ncfet的影响

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510628

B. Obradovic, T. Rakshit, R. Hatcher, J. Kittl, M. Rodder

引用次数: 34

Design Technology Co-Optimization in advanced FDSOI CMOS around the Minimum Energy Point: body biasing and within-cell VT-mixing 围绕最小能量点的先进FDSOI CMOS设计技术协同优化:体偏置和单元内vt混合

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510636

F. Andrieu, L. Pirro, R. Berthelon, J. Morgan, G. Cibrario, M. Wiatr, J. Hoentschel, M. Vinet

引用次数: 2

GeSn p-FinFETs with Sub-10 nm Fin Width Realized on a 200 mm GeSnOI Substrate: Lowest SS of 63 mV/decade, Highest Gm,int of 900 µS/µm, and High-Field µeff of 275 cm2/V•s 在200 mm GeSnOI衬底上实现了小于10 nm翅片宽度的GeSn p- finfet:最低SS为63 mV/decade，最高Gm,int为900µS/µm，高场eff为275 cm2/V•S

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510693

D. Lei, Kaizhen Han, K. Lee, Yi-Chiau Huang, Wei Wang, S. Yadav, Annie Kumar, Ying Wu, Huiquan Heliu, Shengqiang Xu, Yuye Kang, Yang Li, E. Kong, C. S. Tan, X. Gong

{"title":"GeSn p-FinFETs with Sub-10 nm Fin Width Realized on a 200 mm GeSnOI Substrate: Lowest SS of 63 mV/decade, Highest Gm,int of 900 µS/µm, and High-Field µeff of 275 cm2/V•s","authors":"D. Lei, Kaizhen Han, K. Lee, Yi-Chiau Huang, Wei Wang, S. Yadav, Annie Kumar, Ying Wu, Huiquan Heliu, Shengqiang Xu, Yuye Kang, Yang Li, E. Kong, C. S. Tan, X. Gong","doi":"10.1109/VLSIT.2018.8510693","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510693","url":null,"abstract":"We report the first GeSn p-FinFETs with sub-10 nm fin width (W<inf>Fin</inf>) enabled by the formation of the first 200 mm GeSn-on-insulator (GeSnOI) substrate and a self-limiting digital etch for accurate control of the fin dimension, achieving a fin with a top width of 5 nm. Owing to the excellent gate control using extremely scaled GeSn fin and the good GeSn fin quality maintained using a device fabrication process with low thermal budget, an SS of 63 mV/decade was achieved at channel length (L<inf>CH</inf>) of 50 nm, which is a record low for Ge-based p-FETs. Furthermore, record high G<inf>m,int</inf> of 900 μS/µm (V<inf>DS</inf> of -0.5 V) and G<inf>m,int</inf>/S<inf>sat</inf> of 10.5 for GeSn p-FETs were achieved. A high high-field hole mobility µ<inf>eff</inf> of 275 cm2/V•s (at inversion carrier density N<inf>inv</inf> of 8×1012 cm-2) was also obtained.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"46 1","pages":"197-198"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81000746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Highly Manufacturable Low Power and High Performance 11LPP Platform Technology for Mobile and GPU Applications 高度可制造的低功耗和高性能11LPP平台技术，用于移动和GPU应用

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510694

H. Kim, B.H. Choi, Y. Lee, J. Ahn, Y. Bang, Y.D. Lim, J. Do, J.H. Jung, T. Song, Y. Yasuda-Masuoka, K. Park, S. Kwon, J. Yoon

引用次数: 6

True 7nm Platform Technology featuring Smallest FinFET and Smallest SRAM cell by EUV, Special Constructs and 3rd Generation Single Diffusion Break 真正的7nm平台技术，具有最小的FinFET和最小的SRAM单元，EUV，特殊结构和第三代单扩散中断

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510682

W. Jeong, S. Maeda, H. Lee, Kw. Lee, T.J. Lee, D. Park, Bs Kim, J. Do, T. Fukai, DJ Kwon, KJ Nam, WJ Rim, Minsik Jang, H.T. Kim, YW Lee, Js Park, Ec Lee, DW Ha, C. Park, H. Cho, S.-M. Jung, H. Kang

引用次数: 26