2018 IEEE Symposium on VLSI Technology最新文献_第9页

Comprehensive Thermal SPICE Modeling of FinFETs and BEOL with Layout Flexibility Considering Frequency Dependent Thermal Time Constant, 3D Heat Flows, Boundary/Alloy Scattering, and Interfacial Thermal Resistance with Circuit Level Reliability Evaluation 考虑频率相关热时间常数、三维热流、边界/合金散射和界面热阻的布局柔性finfet和BEOL的综合热SPICE建模与电路级可靠性评估

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510701

Jhih-Yang Yan, Chia-Che Chung, Sun-Rong Jan, H. H. Lin, W. K. Wan, M. Yang, C. Liu

{"title":"Comprehensive Thermal SPICE Modeling of FinFETs and BEOL with Layout Flexibility Considering Frequency Dependent Thermal Time Constant, 3D Heat Flows, Boundary/Alloy Scattering, and Interfacial Thermal Resistance with Circuit Level Reliability Evaluation","authors":"Jhih-Yang Yan, Chia-Che Chung, Sun-Rong Jan, H. H. Lin, W. K. Wan, M. Yang, C. Liu","doi":"10.1109/VLSIT.2018.8510701","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510701","url":null,"abstract":"Thermal SPICE modeling with distributed R<inf>th</inf>-C<inf>th</inf> network is proposed to provide more accurate AC self-heating (SH) results than two τ<inf>c</inf> and one τ<inf>c</inf> models. The thermal time constant of the hotspot (τhotspot) in FinFETs is frequency dependent, not a constant. The severe SH by boundary/alloy scattering and interfacial thermal resistance (ITR) is included in our SPICE. The modularized components of fins, metals, and IMDs provide device and routing flexibility, without additional FEM simulation. ITR of Si<inf>80</inf>Ge<inf>20</inf>/Si<inf>1-</inf>xGe<inf>x</inf> is calculated by AMM model as the lower bound for SiGe FinFETs. The intrinsic electromigration (EM) improvement of Co interconnect (5X) is countervailed (5X→2.44X) by the increasing T<inf>metal</inf> due to the low thermal conductivity of Co. Different V2 placements on the power line of a ring oscillator (RO) are proposed to lower both the T<inf>j</inf> (FinFET) and T<inf>metal</inf>. The predicted EM MTTF of Co interconnect with the additional heat dissipation by V2 insertion is ~5.65X of W/Cu interconnect.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"54 1","pages":"113-114"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80046459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

VLSI Technology 2018 Preface VLSI Technology 2018前言

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/vlsit.2018.8510663

引用次数: 0

Process Optimization of Perpendicular Magnetic Tunnel Junction Arrays for Last-Level Cache beyond 7 nm Node 7 nm以上节点末级高速缓存垂直磁隧道结阵列工艺优化

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510642

L. Xue, C. Ching, A. Kontos, Jaesoo Ahn, Xiaodong Wang, R. Whig, H. Tseng, J. Howarth, S. Hassan, Hao Chen, M. Bangar, S. Liang, Rongjun Wang, M. Pakala

引用次数: 15

Revolutionizing Cancer Genomic Medicine by AI and Supercomputer with Big Data 利用人工智能和大数据超级计算机革新癌症基因组医学

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510699

S. Miyano

引用次数: 2

First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs 垂直堆叠栅极全方位高应变锗纳米线p- fet的首次演示

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510645

E. Capogreco, L. Witters, H. Arimura, F. Sebaai, C. Porret, A. Hikavyy, R. Loo, A. Milenin, G. Eneman, P. Favia, H. Bender, K. Wostyn, E. Litta, A. Schulze, C. Vrancken, A. Opdebeeck, J. Mitard, R. Langer, F. Holsteyns, N. Waldron, K. Barla, V. De Heyn, D. Mocuta, N. Collaert

引用次数: 11

Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard Cells 超尺度标准电池上横向纳米片的功率性能权衡

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510633

M. Bardon, Y. Sherazi, D. Jang, D. Yakimets, P. Schuddinck, R. Baert, H. Mertens, L. Mattii, B. Parvais, A. Mocuta, D. Verkest

引用次数: 26

Electromigration Effects in Power Grids Characterized Using an On-Chip Test Structure with Poly Heaters and Voltage Tapping Points 用带有聚加热器和电压分接点的片上测试结构表征电网中的电迁移效应

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510638

Chen Zhou, R. Wong, S. Wen, C. Kim

引用次数: 5

3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability 在300毫米晶圆上的3D顺序堆叠平面器件，具有在525°C下加工的替代金属栅无结顶部器件，提高了可靠性

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510705

A. Vandooren, J. Franco, B. Parvais, Z. Wu, L. Witters, A. Walke, W. Li, L. Peng, V. Desphande, F. M. Bufler, N. Rassoul, G. Hellings, G. Jamieson, F. Inoue, G. Verbinnen, K. Devriendt, L. Teugels, N. Heylen, E. Vecchio, T. Zheng, E. Rosseel, W. Vanherle, A. Hikavyy, B. Chan, R. Ritzenthaler, G. Besnard, W. Schwarzenbach, G. Gaudin, I. Radu, B. Nguyen, N. Waldron, V. D. Heyn, D. Mocuta, N. Collaert

引用次数: 16

Self-organized gate stack of Ge nanosphere/SiO2/Si1-xGex enables Ge-based monolithically-integrated electronics and photonics on Si platform Ge纳米球/SiO2/Si1-xGex的自组织栅极堆栈使基于Ge的单片集成电子和光子学在Si平台上实现

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-01-01 DOI: 10.1109/VLSIT.2018.8510695

P. Liao, M. Kuo, C. Tien, Y. -. Chang, P. Hong, T. George, H. Lin, P. W. Li

{"title":"Self-organized gate stack of Ge nanosphere/SiO2/Si1-xGex enables Ge-based monolithically-integrated electronics and photonics on Si platform","authors":"P. Liao, M. Kuo, C. Tien, Y. -. Chang, P. Hong, T. George, H. Lin, P. W. Li","doi":"10.1109/VLSIT.2018.8510695","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510695","url":null,"abstract":"We report the first-of-its-kind, self-organized gate stack of Ge nanosphere (NP) gate/SiO<inf>2</inf>/Si<inf>1-x</inf>Ge<inf>x</inf> channel fabricated in a single oxidation step. Process-controlled tunability of the Ge NP size (5–90nm), SiO<inf>2</inf> thickness (2–4nm), and Ge content (x = 0.65–0.85) and strain engineering (ε<inf>comp</inf> = 1–3%) of the Si<inf>1-x</inf>Ge<inf>x</inf> are achieved. We demonstrated Ge junctionless (JL) n-FETs and photoMOSFETs (PTs) as amplifier and photodetector, respectively, for Ge receivers. L<inf>G</inf> of 75nm JL n-FETs feature I<inf>ON</inf>/I<inf>OFF</inf> > 5×10<sup>8</sup>, I<inf>ON</inf> > 500µA/µm at V<inf>DS</inf> = 1V, T= 80K. Ge-PTs exhibit superior photoresponsivity >1,000A/W and current gain linearity ranging from nW–mW for 850nm illumination. Size-tunable photo-luminescence (PL) of 300–1600nm (NUV-NIR) are observed on 5–100nm Ge NPs. Our gate stack of Ge NP/SiO<inf>2</inf>/Si<inf>1-x</inf>Ge<inf>x</inf> enables a practically achievable building block for monolithically-integrated Ge electronic and photonic ICs (EPICs) on Si.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"520 1","pages":"157-158"},"PeriodicalIF":0.0,"publicationDate":"2018-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77059602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8