L. Xue, C. Ching, A. Kontos, Jaesoo Ahn, Xiaodong Wang, R. Whig, H. Tseng, J. Howarth, S. Hassan, Hao Chen, M. Bangar, S. Liang, Rongjun Wang, M. Pakala
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引用次数: 15
Abstract
This paper demonstrates systematic process optimization of perpendicular magnetic tunnel junction (pMTJ) by hardware, unit-process, and material stack design. TMR of 200% at RA 5 Ohm•µm2, HSAF ~ 8 kOe, and 10-time tunability of Hc were achieved at the film level. After patterning, 10−6 write error rate was reached at 0.4 pJ, VBD was as high as 1600 mV at 20 ns pulse width, and excellent device stability against 400°C BEOL baking was demonstrated. The device performance along with the process capability to make MTJ array at 88 nm pitch provides opportunities for LLC applications.
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