B. Obradovic, T. Rakshit, R. Hatcher, J. Kittl, M. Rodder
{"title":"Ferroelectric Switching Delay as Cause of Negative Capacitance and the Implications to NCFETs","authors":"B. Obradovic, T. Rakshit, R. Hatcher, J. Kittl, M. Rodder","doi":"10.1109/VLSIT.2018.8510628","DOIUrl":null,"url":null,"abstract":"We report on measurements and modeling of FE HfZrO/SiO2 Ferroelectric-Dielectric (FE-DE) FETs which indicate that phenomena attributed to Negative Capacitance can be explained by a delayed response of ferroelectric domain switching. No traversal of the stabilized negative capacitance branch is required. Modeling is used to correlate the hysteretic properties of the ferroelectric material to the measured transient and subthreshold slope (SS) behavior. It is found that steep SS can be understood as a transient phenomenon, present only when significant polarization changes occur. The technological implications of this finding are investigated, and it is found that NCFETs are most likely not suitable for high-performance CMOS logic, due to voltage, frequency, and voltage polarity limitations.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"62 1","pages":"51-52"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"34","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2018.8510628","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 34
Abstract
We report on measurements and modeling of FE HfZrO/SiO2 Ferroelectric-Dielectric (FE-DE) FETs which indicate that phenomena attributed to Negative Capacitance can be explained by a delayed response of ferroelectric domain switching. No traversal of the stabilized negative capacitance branch is required. Modeling is used to correlate the hysteretic properties of the ferroelectric material to the measured transient and subthreshold slope (SS) behavior. It is found that steep SS can be understood as a transient phenomenon, present only when significant polarization changes occur. The technological implications of this finding are investigated, and it is found that NCFETs are most likely not suitable for high-performance CMOS logic, due to voltage, frequency, and voltage polarity limitations.