Highly Manufacturable Low Power and High Performance 11LPP Platform Technology for Mobile and GPU Applications

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI:10.1109/VLSIT.2018.8510694

H. Kim, B.H. Choi, Y. Lee, J. Ahn, Y. Bang, Y.D. Lim, J. Do, J.H. Jung, T. Song, Y. Yasuda-Masuoka, K. Park, S. Kwon, J. Yoon

引用次数: 6

Abstract

11nm bulk FinFET process employing 3rd generation 14nm FEOL and 10nm BEOL process has been successfully demonstrated with updated design rules for optimal design kit support with 6.75T library. Compared to 14nm 1st generation FinFET, device performance has been improved by 25% in ring oscillator AC frequency at same Iddq or 42% power reduction is achieved. Adopting already mature 14nm and 10nm process technology, we can setup and demonstrate fast yield ramp.

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高度可制造的低功耗和高性能11LPP平台技术，用于移动和GPU应用

采用第3代14纳米FEOL和10纳米BEOL工艺的11纳米体FinFET工艺已成功演示，并更新了设计规则，以优化设计套件支持6.75T库。与14nm第一代FinFET相比，在相同Iddq的环形振荡器交流频率下，器件性能提高了25%，功耗降低了42%。采用已经成熟的14nm和10nm制程技术，我们可以建立和演示快速良率斜坡。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2018 IEEE Symposium on VLSI Technology

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