具有低功耗和高性能应用的第二代FinFET的12nm FinFET技术

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI:10.1109/VLSIT.2018.8510632

H. Lo, D. Choi, Y. Hu, Y. Shen, Y. Qi, J. Peng, D. Zhou, M. Mohan, C. Yong, H. Zhan, H. Wei, X. He, D. Kang, A. Sirman, Y. Wang, H. Zang, S. Mun, A. Vinslava, W.H. Chen, C. Gaire, J. Liu, X. Dou, Y. Shi, P. Zhao, B. Zhu, A. Jha, X. Zhang, X. Wan, E. Lavigne, C. Kyono, M. Togo, J. Versaggi, H. Yu, O. Hu, J. lee, S. Samavedam, D. K. Sohn

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引用次数: 4

摘要

我们提出了一种最先进的12LP FinFET技术，其PPA(性能，功率和面积)优于14LPP。12LP可使面积减小10%，包括7.5T库，在固定频率下功耗降低16%，在14LPP给定泄漏时性能提高15%，具有相当的可靠性和成品率。此外，在相同的Iread下，sram的泄漏减少了30%。12LP扩展了14nm技术，具有引人注目的性能和面积缩放。

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A 12nm FinFET Technology Featuring 2nd Generation FinFET for Low Power and High Performance Applications

We present a state-of-art 12LP FinFET technology with PPA (Performance, Power, and Area) improvement over 14LPP. 12LP enables >10% area reduction including a 7.5T library and 16% power reduction at fixed frequency or a 15% performance improvement at given leakage over 14LPP with comparable reliability and yield. In addition, SRAMs benefit from a 30% leakage reduction at the same Iread. 12LP extends the 14nm technology with compelling performance and area scaling.

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2018 IEEE Symposium on VLSI Technology

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