2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献_第9页

A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks 面向激光攻击RTL建模的基于锥划分的多故障注入方法

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE2014.219

Athanasios Papadimitriou, D. Hély, V. Beroulle, P. Maistri, R. Leveugle

引用次数: 26

Context aware power management for motion-sensing body area network nodes 上下文感知电源管理的体感区域网络节点

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.183

Filippo Casamassima, Elisabetta Farella, L. Benini

引用次数: 19

COOLIP: Simple yet effective job allocation for distributed thermally-throttled processors COOLIP:用于分布式热节流处理器的简单而有效的作业分配

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.293

Pratyush Kumar, Hoeseok Yang, Iuliana Bacivarov, L. Thiele

引用次数: 5

Library-based scalable refinement checking for contract-based design 基于库的可扩展细化检查，用于基于契约的设计

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE2014.167

Antonio Iannopollo, P. Nuzzo, S. Tripakis, A. Sangiovanni-Vincentelli

引用次数: 24

Cross-correlation of specification and RTL for soft IP analysis 软IP分析中规格与RTL的相互关系

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.303

B. Singh, Arunprasath Shankar, F. Wolff, C. Papachristou, D. Weyer, Steve Clay

引用次数: 9

A flexible ASIP architecture for connected components labeling in embedded vision applications 嵌入式视觉应用中连接组件标签的灵活的ASIP体系结构

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.367

Juan Fernando Eusse Giraldo, R. Leupers, G. Ascheid, Patrick Sudowe, B. Leibe, Tamon Sadasue

{"title":"A flexible ASIP architecture for connected components labeling in embedded vision applications","authors":"Juan Fernando Eusse Giraldo, R. Leupers, G. Ascheid, Patrick Sudowe, B. Leibe, Tamon Sadasue","doi":"10.7873/DATE.2014.367","DOIUrl":"https://doi.org/10.7873/DATE.2014.367","url":null,"abstract":"Real-time identification of connected regions of pixels in large (e.g. FullHD) frames is a mandatory and expensive step in many computer vision applications that are becoming increasingly popular in embedded mobile devices such as smart-phones, tablets and head mounted devices. Standard off-the-shelf embedded processors are not yet able to cope with the performance/flexibility trade-offs required by such applications. Therefore, in this work we present an Application Specific Instruction Set Processor (ASIP) tailored to concurrently execute thresholding, connected components labeling and basic feature extraction of image frames. The proposed architecture is capable to cope with frame complexities ranging from QCIF to FullHD frames with 1 to 4 bytes-per-pixel formats, while achieving an average frame rate of 30 frames-per-second (fps). Synthesis was performed for a standard 65nm CMOS library, obtaining an operating frequency of 350MHz and 2.1mm2 area. Moreover, evaluations were conducted both on typical and synthetic data sets, in order to thoroughly assess the achievable performance. Finally, an entire planar-marker based augmented reality application was developed and simulated for the ASIP.","PeriodicalId":6550,"journal":{"name":"2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"9 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79547022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Effective post-silicon failure localization using dynamic program slicing 基于动态程序切片的有效硅后失效定位

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.332

Ophir Friedler, W. Kadry, A. Morgenshtein, Amir Nahir, V. Sokhin

{"title":"Effective post-silicon failure localization using dynamic program slicing","authors":"Ophir Friedler, W. Kadry, A. Morgenshtein, Amir Nahir, V. Sokhin","doi":"10.7873/DATE.2014.332","DOIUrl":"https://doi.org/10.7873/DATE.2014.332","url":null,"abstract":"In post-silicon functional validation, one of the most complex and time-consuming processes is the localization of an instruction that exposes a bug detected at system level. The task is particularly difficult due to the silicon's limited observability and the long time between a failure's occurrence and its detection. We propose a novel method that automates the architectural localization of post-silicon test-case failures. Our proposed tool analyzes a failing test-case, while leveraging the information derived from executing the test on an Instruction Set software Simulator (ISS), to identify a set of instructions that could lead to the faulty final state. The proposed failure localization process comprises the creation of a resource dependency graph based on the execution of the test-case on the ISS, determining a program slice of instructions that influence the faulty resources, and the reduction of the set of suspicious instructions by leveraging the knowledge of the correct resources. We evaluate our proposed solution through extensive experiments. Experimental results show that, in over 97% of all cases, our method was able to narrow down the list of suspicious instructions to under 2 instructions, on average, out of over 200. In over 59% of all cases, our method correctly reduced a test-case to a single faulty instruction.","PeriodicalId":6550,"journal":{"name":"2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"23 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84350365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

DCM: An IP for the autonomous control of optical and electrical reconfigurable NoCs DCM:用于自主控制光和电可重构noc的IP

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.322

Wolfgang Büter, Christof Osewold, Daniel Gregorek, A. Ortiz

引用次数: 4

Word-line power supply selector for stability improvement of embedded SRAMs in high reliability applications 在高可靠性应用中提高嵌入式sram稳定性的字行电源选择器

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.5555/2616606.2616804

B. Alorda, C. Carmona, S. Bota

引用次数: 7

Image progressive acquisition for hardware systems 用于硬件系统的图像渐进采集

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.5555/2616606.2617107

Jianxiong Liu, C. Bouganis, P. Cheung

{"title":"Image progressive acquisition for hardware systems","authors":"Jianxiong Liu, C. Bouganis, P. Cheung","doi":"10.5555/2616606.2617107","DOIUrl":"https://doi.org/10.5555/2616606.2617107","url":null,"abstract":"As the resolution of digital images increases, accessing raw image data from memory has become a major consideration during the design of image/video processing systems. This is due to the fact that the bandwidth requirement and energy consumption of such image accessing process has increased. Inspired by the successful application of progressive image sampling techniques in many image processing tasks, this work proposes to apply similar concept within hardware systems to efficiently trade image quality for reduced memory bandwidth requirement and lower energy consumption. Based on this idea, a hardware system is proposed that is placed between the memory subsystem and the processing core of the design. The proposed system alters the conventional memory access pattern to progressively and adaptively access pixels from a target memory external to the system. The sampled pixels are used to reconstruct an approximation to the ground truth, which is stored in an internal image buffer for further processing. The system is prototyped on FPGA and its performance evaluation shows that a saving of up to 85% of memory accessing time and 33%/45% of image acquisition time/energy is achieved on the benchmark image “lena” while maintaining a PSNR of about 30 dB.","PeriodicalId":6550,"journal":{"name":"2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"28 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80895940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2