2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献_第8页

Contract-based design of control protocols for safety-critical cyber-physical systems 基于契约的安全关键网络物理系统控制协议设计

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.072

P. Nuzzo, John B. Finn, Antonio Iannopollo, A. Sangiovanni-Vincentelli

{"title":"Contract-based design of control protocols for safety-critical cyber-physical systems","authors":"P. Nuzzo, John B. Finn, Antonio Iannopollo, A. Sangiovanni-Vincentelli","doi":"10.7873/DATE.2014.072","DOIUrl":"https://doi.org/10.7873/DATE.2014.072","url":null,"abstract":"We introduce a platform-based design methodology that addresses the complexity and heterogeneity of cyber-physical systems by using assume-guarantee contracts to formalize the design process and enable realization of control protocols in a hierarchical and compositional manner. Given the architecture of the physical plant to be controlled, the design is carried out as a sequence of refinement steps from an initial specification to a final implementation, including synthesis from requirements and mapping of higher-level functional and nonfunctional models into a set of candidate solutions built out of a library of components at the lower level. Initial top-level requirements are captured as contracts and expressed using linear temporal logic (LTL) and signal temporal logic (STL) formulas to enable requirement analysis and early detection of inconsistencies. Requirements are then refined into a controller architecture by combining reactive synthesis steps from LTL specifications with simulation-based design space exploration steps. We demonstrate our approach on the design of embedded controllers for aircraft electric power distribution.","PeriodicalId":6550,"journal":{"name":"2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"11 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87917151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23

Minimizing state-of-health degradation in hybrid electrical energy storage systems with arbitrary source and load profiles 具有任意源和负载轮廓的混合储能系统中健康状态退化的最小化

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE2014.123

Yanzhi Wang, X. Lin, Q. Xie, N. Chang, Massoud Pedram

引用次数: 30

Model-based protocol log generation for testing a telecommunication test harness using CLP 用于使用CLP测试电信测试工具的基于模型的协议日志生成

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.203

K. Balck, Olga Grinchtein, J. Pearson

引用次数: 8

COOLIP: Simple yet effective job allocation for distributed thermally-throttled processors COOLIP:用于分布式热节流处理器的简单而有效的作业分配

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.293

Pratyush Kumar, Hoeseok Yang, Iuliana Bacivarov, L. Thiele

引用次数: 5

The schedulability region of two-level mixed-criticality systems based on EDF-VD 基于EDF-VD的两级混合临界系统的可调度区域

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.269

D. Müller, Alejandro Masrur

引用次数: 10

Context aware power management for motion-sensing body area network nodes 上下文感知电源管理的体感区域网络节点

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.183

Filippo Casamassima, Elisabetta Farella, L. Benini

引用次数: 19

EDT: A specification notation for reactive systems EDT:反应系统的规范符号

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.228

R. Venkatesh, U. Shrotri, G. M. Krishna, Supriya Agrawal

{"title":"EDT: A specification notation for reactive systems","authors":"R. Venkatesh, U. Shrotri, G. M. Krishna, Supriya Agrawal","doi":"10.7873/DATE.2014.228","DOIUrl":"https://doi.org/10.7873/DATE.2014.228","url":null,"abstract":"Requirements of reactive systems express the relationship between sensors and actuators and are usually described in a natural language and a mix of state-based and stream-based paradigms. Translating these into a formal language is an important pre-requisite to automate the verification of requirements. The analysis effort required for the translation is a prime hurdle to formalization gaining acceptance among software engineers and testers. We present Expressive Decision Tables (EDT), a novel formal notation designed to reduce the translation efforts from both state-based and stream-based informal requirements. We have also built a tool, EDTTool, to generate test data and expected output from EDT specifications. In a case study consisting of more than 200 informal requirements of a real-life automotive application, translation of the informal requirements into EDT needed 43% lesser time than their translation into Statecharts. Further, we tested the Statecharts using test data generated by EDTTool from the corresponding EDT specifications. This testing detected one bug in a mature feature and exposed several missing requirements in another. The paper presents the EDT notation, comparison to other similar notations and the details of the case study.","PeriodicalId":6550,"journal":{"name":"2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"153 9 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83135160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Video analytics using beyond CMOS devices 视频分析使用超越CMOS器件

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.357

N. Vijaykrishnan, S. Datta, G. Cauwenberghs, D. Chiarulli, S. Levitan, H. P. Wong

引用次数: 12

Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks 针对供应链攻击的嵌入式可重构ASIC设计混淆逻辑

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE2014.256

Bao Liu, Brandon Wang

{"title":"Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks","authors":"Bao Liu, Brandon Wang","doi":"10.7873/DATE2014.256","DOIUrl":"https://doi.org/10.7873/DATE2014.256","url":null,"abstract":"Hardware is the foundation and the root of trust of any security system. However, in today's global IC industry, an IP provider, an IC design house, a CAD company, or a foundry may subvert a VLSI system with back doors or logic bombs. Such a supply chain adversary's capability is rooted in his knowledge on the hardware design. Successful hardware design obfuscation would severely limit a supply chain adversary's capability if not preventing all supply chain attacks. However, not all designs are obfuscatable in traditional technologies. We propose to achieve ASIC design obfuscation based on embedded reconfigurable logic which is determined by the end user and unknown to any party in the supply chain. Combined with other security techniques, embedded reconfigurable logic can provide the root of ASIC design obfuscation, data confidentiality and tamper-proofness. As a case study, we evaluate hardware-based code injection attacks and reconfiguration-based instruction set obfuscation based on an open source SPARC processor LEON2. We prevent program monitor Trojan attacks and increase the area of a minimum code injection Trojan with a 1KB ROM by 2.38% for every 1% area increase of the LEON2 processor.","PeriodicalId":6550,"journal":{"name":"2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"39 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80077795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 81

Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip 片上网络中一对多通信的线面波混合架构

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.287

Ammar Karkar, Nizar Dahir, Ra'ed Al-Dujaily, K. Tong, T. Mak, A. Yakovlev

{"title":"Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip","authors":"Ammar Karkar, Nizar Dahir, Ra'ed Al-Dujaily, K. Tong, T. Mak, A. Yakovlev","doi":"10.7873/DATE.2014.287","DOIUrl":"https://doi.org/10.7873/DATE.2014.287","url":null,"abstract":"Network-on-chip (NoC) is a communication paradigm that has emerged to tackle different on-chip challenges and has satisfied different demands in terms of high performance and economical interconnect implementation. However, merely metal based NoC pursuit offers limited scalability with the relentless technology scaling, especially in one-to-many (1-to-M) communication. To meet the scalability demand, this paper proposes a new hybrid architecture empowered by both metal interconnects and Zenneck surface wave interconnects (SWI). This architecture, in conjunction with newly proposed routing and global arbitration schemes, avoids overloading the NoC and alleviates traffic hotspots compared to the trend of handling 1-to-M traffic as unicast. This work addresses the system level challenges for intra chip multicasting. Evaluation results, based on a cycle-accurate simulation and hardware description, demonstrate the effectiveness of the proposed architecture in terms of power reduction ratio of 4 to 12X and average delay reduction of 25X or more, compared to a regular NoC. These results are achieved with negligible hardware overheads.","PeriodicalId":6550,"journal":{"name":"2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"320 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80207155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20