2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献_第10页

Scalability bottlenecks discovery in MPSoC platforms using data mining on simulation traces 在模拟轨迹上使用数据挖掘发现MPSoC平台的可扩展性瓶颈

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.199

S. Lagraa, A. Termier, F. Pétrot

引用次数: 13

GPU-EvR: Run-time event based real-time scheduling framework on GPGPU platform GPU-EvR: GPGPU平台上基于运行时事件的实时调度框架

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.233

Haeseung Lee, M. A. Faruque

引用次数: 29

Energy efficient MIMO processing: A case study of opportunistic run-time approximations 节能MIMO处理:机会运行时近似的案例研究

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.220

D. Novo, Nazanin Farahpour, P. Ienne, U. Ahmad, F. Catthoor

引用次数: 2

A multi banked — Multi ported — Non blocking shared L2 cache for MPSoC platforms 一个多银行-多端口-非阻塞共享L2缓存的MPSoC平台

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.093

Igor Loi, L. Benini

{"title":"A multi banked — Multi ported — Non blocking shared L2 cache for MPSoC platforms","authors":"Igor Loi, L. Benini","doi":"10.7873/DATE.2014.093","DOIUrl":"https://doi.org/10.7873/DATE.2014.093","url":null,"abstract":"On-chip L2 cache architectures, well established in high-performance parallel computing systems, are now becoming a performance-critical component also for multi/many-core architectures targeted at lower-power, embedded applications. The very stringent requirements on power and cost of these systems result in one of the key challenges in many-core designs, mandating the deployment of highly efficient L2 caches. In this perspective, sharing the L2 cache layer among all system cores has important advantages, such as increased utilization, fast inter-core communication, and reduced aggregate footprint because no undesired replication of lines occurs. This paper presents a novel architecture for a shared L2 cache system with multi-port and multi-bank features. We target this L2 cache to a many-core platform based on hierarchical cluster structure that does not employ private data caches, and therefore does not require complex coherency mechanisms. In fact, our shared L2 cache can be seen logically as a Last Level Cache (LLC) adopting the terminology of higher-performance many-core products, although in these latter the LLC is more often an L3 layer. Our experimental results show a maximum aggregate bandwidth of 28GB/s (89% of the maximum channel capacity) for 100% hit traffic with random banking conflicts, as a realistic case. Physical implementation results in 28nm Fully-Depleted-Silicon-on-Insulator (FDSoI) show that our L2 cache can operate at up to 1GHz with a memory density loss of only 20% with respect to an L2 scratchpad for a 2 MB configuration.","PeriodicalId":6550,"journal":{"name":"2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"66 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85066097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

The schedulability region of two-level mixed-criticality systems based on EDF-VD 基于EDF-VD的两级混合临界系统的可调度区域

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.269

D. Müller, Alejandro Masrur

引用次数: 10

Contract-based design of control protocols for safety-critical cyber-physical systems 基于契约的安全关键网络物理系统控制协议设计

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.072

P. Nuzzo, John B. Finn, Antonio Iannopollo, A. Sangiovanni-Vincentelli

{"title":"Contract-based design of control protocols for safety-critical cyber-physical systems","authors":"P. Nuzzo, John B. Finn, Antonio Iannopollo, A. Sangiovanni-Vincentelli","doi":"10.7873/DATE.2014.072","DOIUrl":"https://doi.org/10.7873/DATE.2014.072","url":null,"abstract":"We introduce a platform-based design methodology that addresses the complexity and heterogeneity of cyber-physical systems by using assume-guarantee contracts to formalize the design process and enable realization of control protocols in a hierarchical and compositional manner. Given the architecture of the physical plant to be controlled, the design is carried out as a sequence of refinement steps from an initial specification to a final implementation, including synthesis from requirements and mapping of higher-level functional and nonfunctional models into a set of candidate solutions built out of a library of components at the lower level. Initial top-level requirements are captured as contracts and expressed using linear temporal logic (LTL) and signal temporal logic (STL) formulas to enable requirement analysis and early detection of inconsistencies. Requirements are then refined into a controller architecture by combining reactive synthesis steps from LTL specifications with simulation-based design space exploration steps. We demonstrate our approach on the design of embedded controllers for aircraft electric power distribution.","PeriodicalId":6550,"journal":{"name":"2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"11 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87917151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23

Minimizing state-of-health degradation in hybrid electrical energy storage systems with arbitrary source and load profiles 具有任意源和负载轮廓的混合储能系统中健康状态退化的最小化

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE2014.123

Yanzhi Wang, X. Lin, Q. Xie, N. Chang, Massoud Pedram

引用次数: 30

Model-based protocol log generation for testing a telecommunication test harness using CLP 用于使用CLP测试电信测试工具的基于模型的协议日志生成

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.203

K. Balck, Olga Grinchtein, J. Pearson

引用次数: 8

Brisk and limited-impact NoC routing reconfiguration 快速和有限影响的NoC路由重新配置

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE2014.319

Doowon Lee, Ritesh Parikh, V. Bertacco

{"title":"Brisk and limited-impact NoC routing reconfiguration","authors":"Doowon Lee, Ritesh Parikh, V. Bertacco","doi":"10.7873/DATE2014.319","DOIUrl":"https://doi.org/10.7873/DATE2014.319","url":null,"abstract":"The expected low reliability of the silicon substrate at upcoming technology nodes presents a key challenge for digital system designers. Networks-on-chip (NoCs) are especially concerning because they are often the only communication infrastructure for the chips in which they are deployed. Recently, routing reconfiguration solutions have been proposed to address this problem. However, they come at a high silicon cost, and often require suspending the normal network activity while executing a centralized, resource-hungry reconfiguration algorithm. This paper proposes a novel, fast and minimalistic routing reconfiguration algorithm, called BLINC. BLINC utilizes pre-computed routing metadata to quickly evaluate localized detours upon each fault manifestation. We showcase the efficacy of our algorithm by deploying it in a novel NoC fault detection and reconfiguration solution, where BLINC enables uninterrupted NoC operation during aggressive online testing. If a fault seems likely to occur, we circumvent it in advance with the aid of our BLINC reconfiguration algorithm. Experimental results show an 80% reduction in the average number of routers affected by a reconfiguration event, compared to state-of-the-art techniques. BLINC enables negligible performance degradation in our detection and reconfiguration solution, while solutions based on current techniques suffer a 17-fold latency increase.","PeriodicalId":6550,"journal":{"name":"2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"222 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75640317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

Time-decoupled parallel SystemC simulation 时间解耦并行系统仿真

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.204

Jan Weinstock, Christoph Schumacher, R. Leupers, G. Ascheid, L. Tosoratto

引用次数: 29