发布求助
文献互助 智能选刊 最新文献

2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)最新文献

筛选
英文 中文
Wafer level metallic bonding: Voiding mechanisms in copper layers 晶圆级金属键合:铜层中的空化机制
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM) Pub Date : 2015-11-12 DOI: 10.1109/IITC-MAM.2015.7325619
B. Imbert, P. Gondcharton, L. Benaissa, F. Fournel, M. Verdier
{"title":"Wafer level metallic bonding: Voiding mechanisms in copper layers","authors":"B. Imbert, P. Gondcharton, L. Benaissa, F. Fournel, M. Verdier","doi":"10.1109/IITC-MAM.2015.7325619","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325619","url":null,"abstract":"Promoted by the component miniaturization trend, three-dimensional integration appears as a promising option for implementation of the next generation of integrated circuits. In this context, copper is still an interesting material to be integrated to vertical interconnexion through direct metal-metal bonding processes. However, it was already reported that voiding phenomena occur in bonded copper layers for temperature beyond 300°C leading to serious reliability problems. This paper aims at explaining voiding mechanisms in the specific metal bonding configuration. Voiding characteristics are compared in different structures allows highlighting several thermal effects. It appears that the mechanical stress sustained by copper layers during post-bonding thermal processes is the main contribution in the voiding phenomenon. Creep mechanisms occurring in polycrystalline copper structure could be considered as the origin of this phenomenon. This study offers better understanding of reliability problems in structures involving encapsulated copper layers and can be used as guideline for metal bonding integration.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"22 1","pages":"201-204"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84469987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
High-voltage monolithic 3D capacitors based on through-silicon-via technology 基于硅通孔技术的高压单片三维电容器
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM) Pub Date : 2015-11-12 DOI: 10.1109/IITC-MAM.2015.7325655
S. Gruenler, G. Rattmann, T. Erlbacher, A. Bauer, L. Frey
{"title":"High-voltage monolithic 3D capacitors based on through-silicon-via technology","authors":"S. Gruenler, G. Rattmann, T. Erlbacher, A. Bauer, L. Frey","doi":"10.1109/IITC-MAM.2015.7325655","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325655","url":null,"abstract":"High-voltage monolithic 3D capacitors operating at breakdown voltages up to 200 V are fabricated based on through silicon-via technology. Electric characteristics of monolithic 3D capacitors exhibit a capacitance density of 17 times larger than that of planar capacitors with the same area and dielectric thickness. Impact of the 3D capacitors' architecture on their electrical properties is studied for various patterns and geometries.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"11 1","pages":"253-256"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84280105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ni silicides formation: Use of Ge and Pt to study the diffusing species, lateral growth and relaxation mechanisms Ni硅化物的形成:利用Ge和Pt研究其扩散种类、横向生长和弛豫机制
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM) Pub Date : 2015-05-18 DOI: 10.1109/IITC-MAM.2015.7325661
M. El Kousseifi, K. Hoummada, T. Epicier, D. Mangelinck
{"title":"Ni silicides formation: Use of Ge and Pt to study the diffusing species, lateral growth and relaxation mechanisms","authors":"M. El Kousseifi, K. Hoummada, T. Epicier, D. Mangelinck","doi":"10.1109/IITC-MAM.2015.7325661","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325661","url":null,"abstract":"The Ni silicide formation was studied by in situ X-ray diffraction, APT and TEM through the use of either a thin layer of Ge (1 nm) deposited between the Ni film and a Si substrate or a Ni(10%Pt) film. The Ge was used as a marker for the diffusing species during Ni silicide formation and the Ni(10%Pt) allows revealing the lateral growth of NiSi.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"37 1","pages":"257-260"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74002256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Full 3D reciprocal space map of thin polycrystalline films for microelectronic applications 用于微电子应用的多晶薄膜的全三维互反空间图
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM) Pub Date : 2015-05-18 DOI: 10.1109/IITC-MAM.2015.7325624
T. Thanh, N. Blanc, N. Boudet, E. Bourjot, S. Zhiou, V. Kovacova, P. Rodriguez, F. Nemouchi, P. Gergaud
{"title":"Full 3D reciprocal space map of thin polycrystalline films for microelectronic applications","authors":"T. Thanh, N. Blanc, N. Boudet, E. Bourjot, S. Zhiou, V. Kovacova, P. Rodriguez, F. Nemouchi, P. Gergaud","doi":"10.1109/IITC-MAM.2015.7325624","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325624","url":null,"abstract":"We introduce a full 3D reciprocal space map (RSM) measurement technique developed at the BM02 beamline (ESRF) in the framework of ultrathin polycrystalline films for microelectronic applications. This technique gives a complete overview of the reciprocal space in a large range of Bragg angles to detect and characterize the nature and texture of all phases present in a polycrystalline film. As a demonstration for this technique we have performed 3D RSM measurement on several kinds of samples: Ni-based germano-silicide on silicon for source/drain contacts in the framework of sub-20 nm FD-SOI transistors; Ni-based alloyed with III-V materials for power electronics application; and PZT thin films on silicon substrate for MEMS applications. New software (DEVA) is developed in pure Python language in order to quickly automatically and on line treat these multidimensional data, taking into account the specific geometry of our area detector XPAD.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"90 1","pages":"53-56"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74884418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Numerical analysis of airgap stability under process-induced thermo-mechanical loads 过程热机械载荷作用下气隙稳定性的数值分析
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM) Pub Date : 2015-05-18 DOI: 10.1109/IITC-MAM.2015.7325610
H. Zahedmanesh, Mario Gonzalez, I. Ciofi, K. Croes, J. Boemmels, Z. Tokei
{"title":"Numerical analysis of airgap stability under process-induced thermo-mechanical loads","authors":"H. Zahedmanesh, Mario Gonzalez, I. Ciofi, K. Croes, J. Boemmels, Z. Tokei","doi":"10.1109/IITC-MAM.2015.7325610","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325610","url":null,"abstract":"In order to understand the state of process induced stresses in air-gap interconnect structures fabricated by means of etch-back procedure, finite element (FE) models of a 90nm pitch interconnect were developed and stress analysis of the structure was conducted as a function of the dielectric liner and metal barrier (MB) thicknesses in a parametric study in order to minimize the risk of mechanical failure. The results identified the sidewall dielectric liner as the critical location where high stresses can result in failure of structures under thermo-mechanical loads. Simulations suggest that optimal mechanical stability is achieved by minimizing the MB thickness and maximizing the thickness of the conformal dielectric liner. The upper limit of the liner thickness however, is dictated by restrictions imposed by interline capacitance which can lead to RC delay.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"24 1","pages":"47-50"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75095245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Progress in thin wire back-end of-line development 细线后端开发的进展
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM) Pub Date : 2015-05-18 DOI: 10.1109/IITC-MAM.2015.7325601
R. Seidel, G. Bonsdorf, E. Clauss, J. Daleiden-, K. Donegan, F. Feustel, M. Hauschildt, B. Hintze, F. Koschinsky, G. Marxsen, R. Naumann, C. Peters, U. Queitsch, G. Talut, D. Theiss, M. Zinke
{"title":"Progress in thin wire back-end of-line development","authors":"R. Seidel, G. Bonsdorf, E. Clauss, J. Daleiden-, K. Donegan, F. Feustel, M. Hauschildt, B. Hintze, F. Koschinsky, G. Marxsen, R. Naumann, C. Peters, U. Queitsch, G. Talut, D. Theiss, M. Zinke","doi":"10.1109/IITC-MAM.2015.7325601","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325601","url":null,"abstract":"Substantial improvements have been achieved in interconnects with 90nm pitch. Solutions for an optimized patterning and metallization will be presented (e.g. ULK treatments during etch, complete metal hard-mask removal by wet-clean, ultra-thin PVD liner). A particular challenge for a semiconductor foundry is the band-width of customer specific designs and requirements. Novel design dependent process strategies have been developed. Transferring this learning will be crucial for a successful ramp of subsequent technologies.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"51 1","pages":"9-12"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77234888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Direct etched Cu characterization for advanced interconnects 用于高级互连的直接蚀刻Cu表征
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM) Pub Date : 2015-05-18 DOI: 10.1109/IITC-MAM.2015.7325613
L. Wen, F. Yamashita, B. Tang, K. Croes, S. Tahara, Keiichi Shimoda, Takeru Maeshiro, E. Nishimura, F. Lazzarino, I. Ciofi, J. Bommels, Z. Tokei
{"title":"Direct etched Cu characterization for advanced interconnects","authors":"L. Wen, F. Yamashita, B. Tang, K. Croes, S. Tahara, Keiichi Shimoda, Takeru Maeshiro, E. Nishimura, F. Lazzarino, I. Ciofi, J. Bommels, Z. Tokei","doi":"10.1109/IITC-MAM.2015.7325613","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325613","url":null,"abstract":"Cu wires patterning by direct etch methods is investigated at 300mm wafer level. Cross-sectional sidewall profiles with tapering angles around 74.5° are obtained with a mid-line width of 44 nm, which paves the way to further scaling of this technique. Lower resistivity is demonstrated with respect to conventional Cu damascene process, with low leakage current between adjacent Cu lines. An in-situ 10nm SiN cap is deposited as a passivation to enable electrical and reliability tests. The electromigration (EM) characterization shows promising reliability performance of the direct etched Cu wires.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"28 1","pages":"173-176"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76696914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 300mm Si photonics platform for optical interconnection 一种用于光互连的300mm硅光子平台
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM) Pub Date : 2015-05-18 DOI: 10.1109/IITC-MAM.2015.7325665
T. Mogami, T. Horikawa, K. Kinoshita, H. Sasaki, K. Morito, K. Kurata
{"title":"A 300mm Si photonics platform for optical interconnection","authors":"T. Mogami, T. Horikawa, K. Kinoshita, H. Sasaki, K. Morito, K. Kurata","doi":"10.1109/IITC-MAM.2015.7325665","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325665","url":null,"abstract":"The Si photonics platform for 300mm SOI wafers has been built up for optical multi-applications. Main optical devices have been demonstrated. State-of-the-art propagation loss values are obtained for optical waveguides of multi-thickness SOI structures in this platform. The propagation loss is less than 0.5 dB/cm at 1.55pm wavelength for 220nm-thick waveguides. MMI coupler, AWG and WDM filter showed enough high performance for their applications. The 50×50mm2 large Si interposers using photonics electronics convergence technology have been demonstrated. These results indicate that our Si photonics platform is very useful for optical multi-applications.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"150 1","pages":"273-276"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75764531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Evaluation of adhesion energy and its correlation to apparent strength for Cu/SiN interface in copper damascene interconnect structures 铜damascene互连结构中Cu/SiN界面的粘附能及其与表观强度的关系
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM) Pub Date : 2015-05-18 DOI: 10.1109/IITC-MAM.2015.7325649
S. Kamiya, C. Chen, N. Shishido, M. Omiya, K. Koiwa, H. Sato, M. Nishida, T. Nakamura, T. Nokuo, T. Suzuki
{"title":"Evaluation of adhesion energy and its correlation to apparent strength for Cu/SiN interface in copper damascene interconnect structures","authors":"S. Kamiya, C. Chen, N. Shishido, M. Omiya, K. Koiwa, H. Sato, M. Nishida, T. Nakamura, T. Nokuo, T. Suzuki","doi":"10.1109/IITC-MAM.2015.7325649","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325649","url":null,"abstract":"Local apparent strength of interface between copper and cap layer on top was diverse depending on the crystal orientation underneath. For a comprehension of this diversity, physical adhesion energy to separate the interface was evaluated. It essentially does not include mechanical energy dissipating in plastic deformation in the process of crack extension. Sub-micron scale torsion test for elastic-plastic deformation properties and fracture tests on a number of different crystal orientations revealed that difference in adhesion energy is much smaller than difference in plastic dissipation energy. It is highly likely that small difference in the former is intensified through the latter, leading to a huge scatter in strength of LSI interconnect structures.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"44 1","pages":"151-154"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74716869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Nanostructured material formation for beyond Si devices 超硅器件的纳米结构材料形成
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM) Pub Date : 2015-05-18 DOI: 10.1109/IITC-MAM.2015.7325668
H. L. Chang, C. T. Chang, C. Kuo
{"title":"Nanostructured material formation for beyond Si devices","authors":"H. L. Chang, C. T. Chang, C. Kuo","doi":"10.1109/IITC-MAM.2015.7325668","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325668","url":null,"abstract":"Beyond Si CMOS technology is the current challenging for next generation transistor. As demand for nano-scaled devices increase, the ability to manipulate the building blocks of electronic is essential. Catalytic-assisted CNTs are integrated into trenches, holes, parallel plates under CH4/H2 gases by microwave plasma chemical vapor deposition or electron cyclotron resonance deposition. The trench and parallel plates are used to fabricate for gate electrodes, while the holes are used to make interconnections. Results indicate the orientation of grown CNTs is dominated by pattern geometry. The field emission results show that the CNTs exhibit robust electronic properties with emission densities of over ImA/cm2 at 3.97 and 6.30 V/um indicating the high electron emission efficiency as the CNT field effect transistor application. The growth models of Fe, Ni and CoSi2 and application for nanoelectronics are purposed.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"37 1","pages":"285-288"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73955620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信