Progress in thin wire back-end of-line development

Abstract

Substantial improvements have been achieved in interconnects with 90nm pitch. Solutions for an optimized patterning and metallization will be presented (e.g. ULK treatments during etch, complete metal hard-mask removal by wet-clean, ultra-thin PVD liner). A particular challenge for a semiconductor foundry is the band-width of customer specific designs and requirements. Novel design dependent process strategies have been developed. Transferring this learning will be crucial for a successful ramp of subsequent technologies.