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2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)最新文献

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Innovative system on chip platform for Smart Grids and internet of energy applications 面向智能电网和能源互联网应用的创新芯片系统平台
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573498
A. Moscatelli
{"title":"Innovative system on chip platform for Smart Grids and internet of energy applications","authors":"A. Moscatelli","doi":"10.1109/VLSIC.2016.7573498","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573498","url":null,"abstract":"Smart Metering and Smart Grid applications are booming worldwide, requiring innovative integrated circuit solutions to specifically meet multiple and evolving system requirements in terms of connectivity capabilities, system flexibility, sensing accuracy, security, power consumption, system miniaturization and cost of ownership. This paper introduces novel and future-proof system on chip solutions specifically developed to meet these challenging requirements of modern Smart Grid ecosystems.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"13 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82649841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 65nm CMOS transceiver with integrated active cancellation supporting FDD from 1GHz to 1.8GHz at +12.6dBm TX power leakage 一款集成有源对消的65nm CMOS收发器，支持1GHz至1.8GHz的FDD， +12.6dBm TX漏功率
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573499
Sameet Ramakrishnan, Lucas Calderin, A. Puglielli, E. Alon, A. Niknejad, B. Nikolić
{"title":"A 65nm CMOS transceiver with integrated active cancellation supporting FDD from 1GHz to 1.8GHz at +12.6dBm TX power leakage","authors":"Sameet Ramakrishnan, Lucas Calderin, A. Puglielli, E. Alon, A. Niknejad, B. Nikolić","doi":"10.1109/VLSIC.2016.7573499","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573499","url":null,"abstract":"This paper presents an active transmitter (TX) cancellation scheme for FDD that synthesizes a replica of the TX current in shunt with the receiver (RX), virtually shorting out the TX signal for the RX while having minimal impact on TX insertion loss. The prototype in 65nm CMOS demonstrates >50dB cancellation of a +12.6dBm peak 20MHz modulated TX signal. A receiver integrated on the same prototype is able to down-convert the RX signal at 40MHz offset with <;4.3dB noise figure (NF) degradation in the presence of the residual TX.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"74 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83498721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 16-channel noise-shaping machine learning analog-digital interface 一个16通道噪声整形机器学习模拟-数字接口
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573509
Fred N. Buhler, Adam E. Mendrela, Yong Lim, Jeffrey Fredenburg, M. Flynn
{"title":"A 16-channel noise-shaping machine learning analog-digital interface","authors":"Fred N. Buhler, Adam E. Mendrela, Yong Lim, Jeffrey Fredenburg, M. Flynn","doi":"10.1109/VLSIC.2016.7573509","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573509","url":null,"abstract":"A 16-channel machine learning digitizing interface embeds Inner-Product calculation within a Delta-Sigma Modulator (IPDSM) array canceling quantization noise and noise shaping the multiplicand. The prototype, with 16 independent IPDSM channels occupies a core area of 0.95mm2 in 65 nm CMOS. Each channel performs up to 100M multiplications/s. The system is demonstrated with a standard machine learning scheme for image recognition. It achieves the same classification accuracy for the MNIST set of hand-written digits as with the same algorithm on floating point DSP.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"103 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91335769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A fully integrated 144 MHz wireless-power-receiver-on-chip with an adaptive buck-boost regulating rectifier and low-loss H-Tree signal distribution 一个完全集成的144兆赫无线电源接收器芯片与自适应降压升压调节整流器和低损耗h树信号分布
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573492
Chul Kim, Jiwoong Park, Abraham Akinin, S. Ha, R. Kubendran, Hui Wang, P. Mercier, G. Cauwenberghs
{"title":"A fully integrated 144 MHz wireless-power-receiver-on-chip with an adaptive buck-boost regulating rectifier and low-loss H-Tree signal distribution","authors":"Chul Kim, Jiwoong Park, Abraham Akinin, S. Ha, R. Kubendran, Hui Wang, P. Mercier, G. Cauwenberghs","doi":"10.1109/VLSIC.2016.7573492","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573492","url":null,"abstract":"An adaptive buck-boost resonant regulating rectifier (B<sup>2</sup>R<sup>3</sup>) with an integrated on-chip coil and low-loss H-Tree power/signal distribution is presented for efficient and robust wireless power transfer (WPT) over a wide range of input and load conditions. The B<sup>2</sup>R<sup>3</sup> integrated on a 9 mm<sup>2</sup> chip powers integrated neural interfacing circuits as a load, with a TX-load power conversion efficiency of 2.64 % at 10 mm distance, resulting in a WPT system efficiency FoM of 102.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"2014 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73459755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS 一个12位1.6 GS/s的交错SAR ADC，具有双参考移位和插值，在65nm CMOS中实现17.8 fJ/ convstep
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573516
J. Nam, Mohsen Hassanpourghadi, Aoyang Zhang, M. Chen
{"title":"A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS","authors":"J. Nam, Mohsen Hassanpourghadi, Aoyang Zhang, M. Chen","doi":"10.1109/VLSIC.2016.7573516","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573516","url":null,"abstract":"A 12-bit SAR ADC architecture with dual reference shifting and interpolation technique has been proposed and implemented with 8-way time interleaving in 65nm CMOS. The proposed technique converts 4 bits per SAR conversion cycle with reduced overhead, which is a key to achieve both high speed and resolution while maintaining low power consumption. The measured peak SNDR is 72dB and remains above 65.3dB at 1-GHz input frequency at sample rate of 1.6 GS/s. It achieves a record power efficiency of 17.8fJ/conv-step among the recently published high-speed/resolution ADCs.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"117 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77590998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A compact 446 Gbps/W AES accelerator for mobile SoC and IoT in 40nm 紧凑型446 Gbps/W AES加速器，适用于40nm的移动SoC和物联网
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573553
Yiqun Zhang, Kaiyuan Yang, Mehdi Saligane, D. Blaauw, D. Sylvester
{"title":"A compact 446 Gbps/W AES accelerator for mobile SoC and IoT in 40nm","authors":"Yiqun Zhang, Kaiyuan Yang, Mehdi Saligane, D. Blaauw, D. Sylvester","doi":"10.1109/VLSIC.2016.7573553","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573553","url":null,"abstract":"An AES hardware accelerator targeting energy efficient, low cost mobile and IoT applications is fabricated in 40nm CMOS. The proposed design eliminates the ShiftRow stage in conventional AES implementations and replaces flip-flops in data and key storage with latches using re-timing, saving 25% area and 69% power. Along with a 2-stage Sbox in native GF(24)2 composite-field computation and glitch reduction techniques, this results in a compact 2228 gate design achieving 446 Gbps/W and 46.2 Mbps throughput at 0.47V.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83530181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
1.74-µW/ch, 95.3%-accurate spike-sorting hardware based on Bayesian decision 1.74-µW/ch, 95.3%准确率的基于贝叶斯决策的尖峰排序硬件
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573468
Zhewei Jiang, J. P. Cerqueira, Seongjong Kim, Qi Wang, Mingoo Seok
{"title":"1.74-µW/ch, 95.3%-accurate spike-sorting hardware based on Bayesian decision","authors":"Zhewei Jiang, J. P. Cerqueira, Seongjong Kim, Qi Wang, Mingoo Seok","doi":"10.1109/VLSIC.2016.7573468","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573468","url":null,"abstract":"This paper presents algorithm/hardware co-design for real-time unsupervised spike sorting hardware for reducing power and improving sorting accuracy. We devise an algorithm based on Bayesian decision, which enables high accuracy while using noisy and simple time-domain features. Those simple features significantly reduce computation complexity, memory requirement, and thus the required number of cycles per sorting. The latter, coupled with the sparsity of spikes in time, makes the hardware idle for most of time, and thus we employ aggressive power gating and balloon latches to sleep most of the circuits and wake them up only when a spike is detected for maximal power savings. The hardware prototyped in a 65nm achieves higher accuracy at lower power than the existing arts.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"23 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90729444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 0.6mW 31MHz 4th-order low-pass filter with +29dBm IIP3 using self-coupled source follower based biquads in 0.18µm CMOS 一个0.6mW 31MHz 4阶低通滤波器，+29dBm IIP3，使用基于自耦合源跟随器的biquad, 0.18µm CMOS
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573507
Yang Xu, Spencer Leuenberger, Praveen Kumar Venkatachala, U. Moon
{"title":"A 0.6mW 31MHz 4th-order low-pass filter with +29dBm IIP3 using self-coupled source follower based biquads in 0.18µm CMOS","authors":"Yang Xu, Spencer Leuenberger, Praveen Kumar Venkatachala, U. Moon","doi":"10.1109/VLSIC.2016.7573507","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573507","url":null,"abstract":"A highly compact low-pass filter (LPF) using self-coupled source follower based biquads is presented. The biquad cell synthesizes a 2nd-order low-pass transfer function in a single branch, using only two capacitors and a source follower with embedded local feedback for excellent linearity. A 4th-order Chebyshev LPF prototype is designed with a cascade of two biquads in 0.18μm CMOS, and occupies an active area of 0.1mm2. A cut-off frequency of 31MHz is measured with a stop-band rejection of 76dB. The prototype filter draws only 0.46mA current from a 1.35V supply, and achieves an in-band IIP3 of +29dBm. The averaged in-band input-referred noise is 22.8nV/√Hz, resulting in a dynamic range of 71dB.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"54 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80606552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
An inductor-less fractional-N injection-locked PLL with a spur-and-phase-noise filtering technique 采用脉冲和相位噪声滤波技术的无电感分数n注入锁相环
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573547
A. Li, Y. Chao, Xuan Chen, Liang Wu, H. Luong
{"title":"An inductor-less fractional-N injection-locked PLL with a spur-and-phase-noise filtering technique","authors":"A. Li, Y. Chao, Xuan Chen, Liang Wu, H. Luong","doi":"10.1109/VLSIC.2016.7573547","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573547","url":null,"abstract":"Utilizing a novel phase-averaging filtering technique capable of wide-band spur-and-phase-noise suppression of up to 20dB, a 1.2-GHz inductor-less fractional-N injection-locked PLL achieves phase noise as low as -146dBc/Hz at 30MHz offset with 2MHz resolution allowing for inductor-less alternatives to LC-based PLLs in wireless applications. The 65nm CMOS prototype improves 10-MHz phase noise from -115 to -135dBc/Hz, injection spurs from -40.5dB to -57dB, and integrated jitter from 3.57ps to 1.48ps while occupying an area of 0.6mm2 and consuming 19.8mW from a 0.85V supply resulting in FoM and FoMJitter of -163dB and -223.6dB respectively.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"40 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85276600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 400mV active VMIN, 200mV retention VMIN, 2.8 GHz 64Kb SRAM with a 0.09 um2 6T bitcell in a 16nm FinFET CMOS process 一个400mV有源VMIN, 200mV保持VMIN, 2.8 GHz 64Kb SRAM，位单元为0.09 um2 6T，采用16nm FinFET CMOS工艺
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573513
A. Bhavnagarwala, Imran Iqbal, A. Nguyen, David Ondricek, V. Chandra, R. Aitken
{"title":"A 400mV active VMIN, 200mV retention VMIN, 2.8 GHz 64Kb SRAM with a 0.09 um2 6T bitcell in a 16nm FinFET CMOS process","authors":"A. Bhavnagarwala, Imran Iqbal, A. Nguyen, David Ondricek, V. Chandra, R. Aitken","doi":"10.1109/VLSIC.2016.7573513","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573513","url":null,"abstract":"We propose and demonstrate in silicon simple, new circuit solutions using a standard 1-1-2 fin 0.09 um2 6T SRAM commercial bitcell in a 16nm FinFET CMOS process to enable a 400mV active VMIN, 200mV retention VMIN SRAM in a 64Kb CMOS array with 128b/BL. Active VMIN is enabled with a self-triggered feedback on an under-driven BL with faster and more robust signal development on the BL at lower voltages - providing dual read assist, and also a 2X tighter offset voltage distribution when compared to conventional differential voltage sensing. 200mV retention VMIN is enabled by reusing write assist circuit overhead while engaging two key observations: insensitivity of bitcell stability to systematic variations and sensitivity of bitcell data to noise on the power grid in the subthreshold/near threshold region. Average FMAX of 140MHz and 2.8GHz are measured across all chips for VDD at 0.4V and 0.9V respectively.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"75 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86302586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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