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2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)最新文献

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Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes 采用集成分析(UTOPIA)的统一技术优化平台，在<= 7nm节点上进行整体技术、设计和系统协同优化
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573515
S. C. Song, J. Xu, D. Yang, K. Rim, P. Feng, Jerry Bao, J. Zhu, J. Wang, G. Nallapati, M. Badaroglu, P. Narayanasetti, B. Bucki, J. Fischer, G. Yeap
{"title":"Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes","authors":"S. C. Song, J. Xu, D. Yang, K. Rim, P. Feng, Jerry Bao, J. Zhu, J. Wang, G. Nallapati, M. Badaroglu, P. Narayanasetti, B. Bucki, J. Fischer, G. Yeap","doi":"10.1109/VLSIC.2016.7573515","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573515","url":null,"abstract":"We propose complete technology-design-system co-optimization method in which power, performance, thermal, area and cost metrics are all simultaneously optimized from transistor to mobile SOC system level. This novel method, Unified Technology Optimization Platform using Integrated Analysis (UTOPIA), incorporates thermally limited performance, wafer process complexity and die area scaling model in addition to author's previous transistor-interconnect optimization method. Thermal model in UTOPIA evaluates/optimizes device and technology parameters not only for peak frequency but also for sustained performance after thermal throttling. Optimum N7 technology is selected using proposed UTOPIA method, showing significant overall gain over N10 technology.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88144112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 125 mW 8.5–11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOS
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573521
Bharath Raghavan, A. Varzaghani, L. Rao, Henry Park, Xiaochen Yang, Z. Huang, Yu Chen, R. Kattamuri, Chunhui Wu, Bo Zhang, Jun Cao, A. Momtaz, N. Kocaman
{"title":"A 125 mW 8.5–11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOS","authors":"Bharath Raghavan, A. Varzaghani, L. Rao, Henry Park, Xiaochen Yang, Z. Huang, Yu Chen, R. Kattamuri, Chunhui Wu, Bo Zhang, Jun Cao, A. Momtaz, N. Kocaman","doi":"10.1109/VLSIC.2016.7573521","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573521","url":null,"abstract":"This paper describes an 8.5-11.5 Gb/s transceiver with a dual path receiver and a voltage-mode transmitter. The RX can operate either in ADC mode for complex loss channels such as optical multimode fiber or in DFE mode for copper-based backplane links. The ADC path implements a 2X interleaved 6-bit rectifying flash ADC using a programmable gain amplifier (PGA) with controlled bandwidth and peaking, comparator pipelining, and super-source follower circuit techniques. The LRM optical sensitivity requirements are met with a > 6 dB margin while achieving an ENOB of 4.59 bits at a 5 GHz input frequency. The TX/RX DFE path achieves copper channel loss compensation of 38 dB with BER <; 10-12 at 11.5 Gb/s consuming 46mW from a 0.9V supply. The TX/RX ADC path consumes 125 mW at 10.3125 Gb/s. The TX/RX occupies 0.56 mm2 in a 28nm standard CMOS process.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"77 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91187219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback 13.3 mW 60 MHz带宽，76 dB DR 6 GS/s CTΔΣM，时间交错FIR反馈
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573466
Ankesh Jain, S. Pavan
{"title":"A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback","authors":"Ankesh Jain, S. Pavan","doi":"10.1109/VLSIC.2016.7573466","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573466","url":null,"abstract":"We present a wideband single-bit CTΔΣM that uses a 2× time-interleaved quantizer and FIR DAC. Time interleaving reduces power dissipation and regeneration errors of the FIR DAC when compared to a full rate implementation. Fabricated in a low leakage 65nm CMOS, the prototype modulator operates at 6 GS/s and achieves 67.6/76 dB SNDR/DR in a 60 MHz bandwidth while consuming 13.3 mW. The FoM is 56.5 fJ/conv-step.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"50 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76499554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications 超低电压应用的28nm FDSOI技术sub-0.6V SRAM Vmin评估
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573512
R. Ranica, N. Planes, V. Huard, O. Weber, D. Noblet, D. Croain, F. Giner, S. Naudet, P. Mergault, S. Ibars, A. Villaret, M. Parra, S. Haendler, M. Quoirin, F. Cacho, C. Julien, F. Terrier, L. Ciampolini, D. Turgis, C. Lecocq, F. Arnaud
{"title":"28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications","authors":"R. Ranica, N. Planes, V. Huard, O. Weber, D. Noblet, D. Croain, F. Giner, S. Naudet, P. Mergault, S. Ibars, A. Villaret, M. Parra, S. Haendler, M. Quoirin, F. Cacho, C. Julien, F. Terrier, L. Ciampolini, D. Turgis, C. Lecocq, F. Arnaud","doi":"10.1109/VLSIC.2016.7573512","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573512","url":null,"abstract":"Vmin measurements in 28nm FDSOI technology on 128Mb SRAM bitcells from -40°C to 125°C are reported in this paper. Adding the silicon ageing behavior and the process variability, we have developed a complete model and demonstrated end-of-life SRAM Vmin of 0.6V and 0.5V on 20Mb with 0.120μm2 and 0.152μm2 bitcells, respectively. This is the first report of a such extensive SRAM Vmin assessment at the 28nm node. The construction of write limited bitcells, combined with write assist design technique, was found to be the most efficient way to achieve ultra low Vmin in 28nm FDSOI technology. In addition, Vmin retention below 0.4V is demonstrated in 0.120μm2 bitcells, leading to the enablement of ultra-low leakage bitcells with 2pA/cell in retention mode.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"142 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74563588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 0.23 µg bias instability and 1.6 µg/Hz1/2 resolution silicon oscillating accelerometer with build-in Σ-Δ frequency-to-digital converter 一个0.23µg偏置不稳定性和1.6µg/Hz1/2分辨率硅振荡加速度计与内置Σ-Δ频率到数字转换器
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573530
Jian Zhao, Xi Wang, Yang Zhao, G. Xia, A. Qiu, Yan Su, Y. Xu
{"title":"A 0.23 µg bias instability and 1.6 µg/Hz1/2 resolution silicon oscillating accelerometer with build-in Σ-Δ frequency-to-digital converter","authors":"Jian Zhao, Xi Wang, Yang Zhao, G. Xia, A. Qiu, Yan Su, Y. Xu","doi":"10.1109/VLSIC.2016.7573530","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573530","url":null,"abstract":"This paper presents a silicon oscillating accelerometer (SOA) with CMOS readout circuit. To reduce the bias instability, a PLL is employed to sustain the oscillation instead of the conventional auto-amplitude-control (AAC) circuit. A sigma-delta frequency-to-digital converter (FDC) is built in the PLL to produce the digital output. The MEMS sensor and readout circuit are fabricated in 80 μm SOI and standard 0.35 μm CMOS process, respectively. The SOA achieves 0.23 μg bias instability and 1.6 μg/Hz1/2 resolution with ±30 g full-scale, which are equivalent to 4-ppb relative instability and 27-ppb/Hz1/2resolution. In addition, it only consumes 2.7 mW under a 1.5 V supply.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"12 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73184067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Motor Control used to be boring 马达控制过去很无聊
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573495
A. Tessarolo
{"title":"Motor Control used to be boring","authors":"A. Tessarolo","doi":"10.1109/VLSIC.2016.7573495","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573495","url":null,"abstract":"Motor Control may not be as trendy as say IoT, but it cannot be denied that the application areas of late have been much more interesting. The growing popularity of drones, electric vehicles such as the Tesla, mobility vehicles like electric bikes or the allure of hover-boards have seen an explosion of electric motors. But changes are also happening in the more traditional industrial sector of motor and servo drives. The demand for cost and energy efficiency is driving the need for new system topologies and greater integration levels. Devices now have to integrate communications with traditional control. Integrated Safety and Security are now part of the mix. The Motor Control device of today is vastly different then 10+ years ago and the challenges are much greater, requiring a broader set of design skills.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90096347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither 具有背景校准和抖动的14位2.5GS/s和5GS/s射频采样ADC
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573537
Ahmed M. A. Ali, H. Dinç, Paritosh Bhoraskar, S. Puckett, Andrew S. Morgan, Ning Zhu, Q. Yu, C. Dillon, Bryce Gray, Jonathan Lanford, Matthew McShea, Ushma Mehta, S. Bardsley, Peter R. Derounian, R. Bunch, Ralph Moore, Gerry Taylor
{"title":"A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither","authors":"Ahmed M. A. Ali, H. Dinç, Paritosh Bhoraskar, S. Puckett, Andrew S. Morgan, Ning Zhu, Q. Yu, C. Dillon, Bryce Gray, Jonathan Lanford, Matthew McShea, Ushma Mehta, S. Bardsley, Peter R. Derounian, R. Bunch, Ralph Moore, Gerry Taylor","doi":"10.1109/VLSIC.2016.7573537","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573537","url":null,"abstract":"We describe a 14-bit 2.5GS/s non-interleaved pipelined ADC that relies on correlation-based background calibrations to correct the inter-stage gain, settling (dynamic), kick-back and memory errors. A new technique is employed to inject a large dither signal on the input to dither the non-linear kick-back on the ADC driver, and another large dither signal is injected to dither any residual non-linearity in the pipeline. In order to correct the effect of aging on the comparators, a new background calibration technique is employed to correct the comparator offsets. The ADC is fabricated as a dual in a 28nm CMOS process. An optional interleaved mode is provided, where the two ADCs on chip are time-interleaved to obtain a single 14-bit 5GS/s ADC. Background calibration of offset and gain mismatch and fixed calibration of timing mismatch between the two channels are implemented on chip.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"81 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88917363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
A 5.8 pJ/Op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor array 一个5.8 pJ/Op 1150亿ops/秒，到1.78万亿ops/秒的32nm千处理器阵列
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573511
Brent Bohnenstiehl, Aaron Stillmaker, J. Pimentel, Timothy Andreas, Bin Liu, A. Tran, E. Adeagbo, B. Baas
{"title":"A 5.8 pJ/Op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor array","authors":"Brent Bohnenstiehl, Aaron Stillmaker, J. Pimentel, Timothy Andreas, Bin Liu, A. Tran, E. Adeagbo, B. Baas","doi":"10.1109/VLSIC.2016.7573511","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573511","url":null,"abstract":"1000 programmable processors and 12 independent memory modules capable of simultaneously servicing both data and instruction requests are integrated onto a 32nm PD-SOI CMOS device. At 1.1 V, processors operate up to an average of 1.78 GHz yielding a maximum total chip computation rate of 1.78 trillion instructions/sec. At 0.84 V, 1000 cores execute 1 trillion instructions/sec while dissipating 13.1 W.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"47 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81352590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
Versatile TLC NAND flash memory control to reduce read disturb errors by 85% and extend read cycles by 6.7-times of Read-Hot and Cold data for cloud data centers 多功能TLC NAND闪存控制，可减少85%的读干扰错误，并将云数据中心的读热、读冷数据的读周期延长6.7倍
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573505
A. Kobayashi, Tsukasa Tokutomi, K. Takeuchi
{"title":"Versatile TLC NAND flash memory control to reduce read disturb errors by 85% and extend read cycles by 6.7-times of Read-Hot and Cold data for cloud data centers","authors":"A. Kobayashi, Tsukasa Tokutomi, K. Takeuchi","doi":"10.1109/VLSIC.2016.7573505","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573505","url":null,"abstract":"Versatile Triple-Level-Cell (TLC) NAND flash memory control with Read Hot/Cold Migration, Read Voltage Control and Edge Word Line Protection is proposed for data center application SSDs. Measured errors decrease by 85% and measured acceptable read cycles increase by 6.7-times.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"27 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84757564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 190GFLOPS/W DSP for energy-efficient sparse-BLAS in embedded IoT 嵌入式物联网中节能稀疏blas的190GFLOPS/W DSP
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI: 10.1109/VLSIC.2016.7573527
R. Dorrance, D. Markovic
{"title":"A 190GFLOPS/W DSP for energy-efficient sparse-BLAS in embedded IoT","authors":"R. Dorrance, D. Markovic","doi":"10.1109/VLSIC.2016.7573527","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573527","url":null,"abstract":"A DSP for sparse-BLAS is realized in 40nm CMOS. Featuring an efficient data stream reordering scheme and an intelligent, CSC-aware memory controller, the DSP achieves a peak energy efficiency of 190 GFLOPS/W at 0.6V, 160MHz, and a peak performance of 4.12 GFLOPS at 1V, 515MHz showing more than 6,600×, 2,700×, 1,100×, and 450× higher energy efficiency than state-of-the-art CPU, GPU, DSP, and FPGA hardware designs, respectively.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"67 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82117444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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