13.3 mW 60 MHz带宽，76 dB DR 6 GS/s CTΔΣM，时间交错FIR反馈

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI:10.1109/VLSIC.2016.7573466

Ankesh Jain, S. Pavan

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引用次数: 13

摘要

我们提出了一种宽带单比特CTΔΣM，它使用2倍时间交错量化器和FIR DAC。与全速率实现相比，时间交错减少了FIR DAC的功耗和再生错误。该原型调制器采用低漏65nm CMOS制造，工作速度为6 GS/s，在60 MHz带宽下实现67.6/76 dB SNDR/DR，功耗为13.3 mW。FoM为56.5 fJ/反步。

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A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback

We present a wideband single-bit CTΔΣM that uses a 2× time-interleaved quantizer and FIR DAC. Time interleaving reduces power dissipation and regeneration errors of the FIR DAC when compared to a full rate implementation. Fabricated in a low leakage 65nm CMOS, the prototype modulator operates at 6 GS/s and achieves 67.6/76 dB SNDR/DR in a 60 MHz bandwidth while consuming 13.3 mW. The FoM is 56.5 fJ/conv-step.

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2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)

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