采用脉冲和相位噪声滤波技术的无电感分数n注入锁相环

A. Li, Y. Chao, Xuan Chen, Liang Wu, H. Luong
{"title":"采用脉冲和相位噪声滤波技术的无电感分数n注入锁相环","authors":"A. Li, Y. Chao, Xuan Chen, Liang Wu, H. Luong","doi":"10.1109/VLSIC.2016.7573547","DOIUrl":null,"url":null,"abstract":"Utilizing a novel phase-averaging filtering technique capable of wide-band spur-and-phase-noise suppression of up to 20dB, a 1.2-GHz inductor-less fractional-N injection-locked PLL achieves phase noise as low as -146dBc/Hz at 30MHz offset with 2MHz resolution allowing for inductor-less alternatives to LC-based PLLs in wireless applications. The 65nm CMOS prototype improves 10-MHz phase noise from -115 to -135dBc/Hz, injection spurs from -40.5dB to -57dB, and integrated jitter from 3.57ps to 1.48ps while occupying an area of 0.6mm2 and consuming 19.8mW from a 0.85V supply resulting in FoM and FoMJitter of -163dB and -223.6dB respectively.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"40 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"An inductor-less fractional-N injection-locked PLL with a spur-and-phase-noise filtering technique\",\"authors\":\"A. Li, Y. Chao, Xuan Chen, Liang Wu, H. Luong\",\"doi\":\"10.1109/VLSIC.2016.7573547\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Utilizing a novel phase-averaging filtering technique capable of wide-band spur-and-phase-noise suppression of up to 20dB, a 1.2-GHz inductor-less fractional-N injection-locked PLL achieves phase noise as low as -146dBc/Hz at 30MHz offset with 2MHz resolution allowing for inductor-less alternatives to LC-based PLLs in wireless applications. The 65nm CMOS prototype improves 10-MHz phase noise from -115 to -135dBc/Hz, injection spurs from -40.5dB to -57dB, and integrated jitter from 3.57ps to 1.48ps while occupying an area of 0.6mm2 and consuming 19.8mW from a 0.85V supply resulting in FoM and FoMJitter of -163dB and -223.6dB respectively.\",\"PeriodicalId\":6512,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"volume\":\"40 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2016.7573547\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573547","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

摘要

利用一种新颖的相位平均滤波技术,能够抑制高达20dB的宽带脉冲和相位噪声,1.2 ghz无电感分数n注入锁相环在30MHz偏移量下实现低至-146dBc/Hz的相位噪声,分辨率为2MHz,允许无线应用中无电感的lc锁相环替代方案。65nm CMOS原型将10 mhz相位噪声从-115提高到-135dBc/Hz,注入杂散从-40.5dB提高到-57dB,集成抖动从3.57ps提高到1.48ps,而占用0.6mm2的面积和0.85V电源消耗19.8mW,导致FoM和FoMJitter分别为-163dB和-223.6dB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An inductor-less fractional-N injection-locked PLL with a spur-and-phase-noise filtering technique
Utilizing a novel phase-averaging filtering technique capable of wide-band spur-and-phase-noise suppression of up to 20dB, a 1.2-GHz inductor-less fractional-N injection-locked PLL achieves phase noise as low as -146dBc/Hz at 30MHz offset with 2MHz resolution allowing for inductor-less alternatives to LC-based PLLs in wireless applications. The 65nm CMOS prototype improves 10-MHz phase noise from -115 to -135dBc/Hz, injection spurs from -40.5dB to -57dB, and integrated jitter from 3.57ps to 1.48ps while occupying an area of 0.6mm2 and consuming 19.8mW from a 0.85V supply resulting in FoM and FoMJitter of -163dB and -223.6dB respectively.
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