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2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)最新文献

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An exploration of usable authentication mechanisms for virtual reality systems 虚拟现实系统可用认证机制的探索
2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804002
Zhen Yu, Hai-Ning Liang, Charles Fleming, K. Man
{"title":"An exploration of usable authentication mechanisms for virtual reality systems","authors":"Zhen Yu, Hai-Ning Liang, Charles Fleming, K. Man","doi":"10.1109/APCCAS.2016.7804002","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804002","url":null,"abstract":"Usable security for virtual reality systems (VR) is an area that is relatively underexplored. This research investigates the feasibility of some authentication mechanisms for VR. We implemented three password methods including 3D patterns, 2D sliding patterns, and a PIN system within a VR environment. Two experiments were conducted to test the usability and security level of the three password systems. The results suggested that the 3D password system may have the highest security level among the three systems, whereas the pattern lock and PIN systems were likely to be perceived as more usable.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"1 1","pages":"458-460"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82986663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
Test access mechaism for stack test time reduction of 3-dimensional integrated circuit 一种减少三维集成电路堆叠测试时间的测试存取机制
2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804019
Inhyuk Choi, Hyunggoy Oh, Sungho Kang
{"title":"Test access mechaism for stack test time reduction of 3-dimensional integrated circuit","authors":"Inhyuk Choi, Hyunggoy Oh, Sungho Kang","doi":"10.1109/APCCAS.2016.7804019","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804019","url":null,"abstract":"In this paper, the reconfigurable test access mechanism (RTAM) is designed based on the emerging test standard to reduce the cumulative stack test time of the 3-dimensional integrated circuit (3-D IC). The RTAM enables the test scheduling to reflect the variation of the test constraints in the overall stack test phases. Simulation results show the RTAM achieves the cumulative stack test time reduction compared with a non-reconfigurable TAM for the stacked dies in the 3-D IC.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"5 1","pages":"522-525"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84329650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
DC-20 GHz differential transmit/receieve DP4T switching matrix for radar-based target detection 用于雷达目标探测的dc - 20ghz差分发射/接收DP4T切换矩阵
2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804071
A. Azhari, T. Kikkawa
{"title":"DC-20 GHz differential transmit/receieve DP4T switching matrix for radar-based target detection","authors":"A. Azhari, T. Kikkawa","doi":"10.1109/APCCAS.2016.7804071","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804071","url":null,"abstract":"A DC-20 GHz differential transmit/receive (T/R) double-pole-four-throw (DP4T) switching matrix has been developed on standard 65 nm CMOS process for the first time for ultra-wideband radar based tumor detection. The measured input and output matching bandwidth are 0–20 GHz where both the input and output return losses are greater than 10 dB. Measured average insertion loss from Tx or Rx port to different output ports are 2.72 dB, 3.6 dB, 4.5 dB and 5.9 dB at 3 GHz, 6 GHz, 10 GHz and 17 GHz, respectively, with a power consumption of less than 1 mW. When the output ports were connected to PCB connectors, 0–18 GHz matching bandwidth was obtained by flip chip mounting, quarter wavelength microstripline impedance matching and optimization of the thickness and dielectric constant of printed circuit board.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"77 1","pages":"706-709"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90648997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Particle swarm optimization for matrix converter of switching pattern design 基于粒子群算法的矩阵变换器开关模式设计
2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7803961
T. Shindo, K. Jin'no
{"title":"Particle swarm optimization for matrix converter of switching pattern design","authors":"T. Shindo, K. Jin'no","doi":"10.1109/APCCAS.2016.7803961","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803961","url":null,"abstract":"There are several types of switching pattern design of the matrix converter. In this paper, we discuss the switching pattern design of the matrix converter. As a new switching pattern design method, the application of the PSO, which is one of the non-linear optimization method. Further, the switching pattern is confirmed generated from numerical experiments.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"22 1","pages":"309-312"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87652431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A design of a cost-effective look-up table for RGB-to-RGBW conversion rgb到rgbw转换的经济高效查找表的设计
2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7803929
Sunwoong Kim, Hyuk-Jae Lee
{"title":"A design of a cost-effective look-up table for RGB-to-RGBW conversion","authors":"Sunwoong Kim, Hyuk-Jae Lee","doi":"10.1109/APCCAS.2016.7803929","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803929","url":null,"abstract":"RGBW domain is widely used to improve the brightness of display panels without their increasing power consumption. RGBW display systems use a look-up table (LUT) for fast RGB-to-RGBW conversion. However, the LUT is implemented by a large size memory and thereby incurring high hardware cost. To reduce the size of the LUT, data mapping in the LUT are sub-sampled, which results in large errors in data conversion. Based on the piecewise-linear characteristic in color change, the sub-sampled data are linearly interpolated. In addition, the interpolation performance is improved by utilizing distribution patterns of color components. Experimental results show that the average of the mean square errors by the proposed method is 21.72 when the size of the LUT decreases to 1/215 of the original LUT size.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"64 1","pages":"188-191"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88599679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
LEGO-based VLSI design and implementation of polar codes encoder architecture with radix-2 processing engines 基于乐高的VLSI极码编码器结构设计与实现，采用基数2处理引擎
2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804057
Xin-Yu Shih, Po-Chun Huang, Yu-Chun Chen
{"title":"LEGO-based VLSI design and implementation of polar codes encoder architecture with radix-2 processing engines","authors":"Xin-Yu Shih, Po-Chun Huang, Yu-Chun Chen","doi":"10.1109/APCCAS.2016.7804057","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804057","url":null,"abstract":"Polar Codes become a new channel coding, which will be common to apply for next-generation wireless MIMO communication systems. In this work, we propose LEGO-based VLSI hardware design and implementation of the Polar encoder using radix-2 processing engines, which features low area cost, low power dissipation, high speed, and high throughput via serial computation. Under TSMC 90nm CMOS technology, the 16384-point LEGO-based radix-2 Polar encoder chip (LB-R2-PE) is designed and synthesized with total area of 0.244mm2 and power dissipation of 366.6mW, operating at maximum frequency of 2.0GHz. In the APR chip implementation point-of-view, the 16384-point LB-R2-PE chip only occupies 0.305mm2 and consumes 357.8mW with maximum operating frequency of 1.61GHz, delivering total throughput of 1.61Gbps.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"224 1","pages":"577-580"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75565366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A comparative analysis on binary and multiple-unary weighted power stage design for digital LDO 数字LDO中二元和多重一元加权功率级设计的比较分析
2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7803890
Fan Yang, Yasu Lu, P. Mok
{"title":"A comparative analysis on binary and multiple-unary weighted power stage design for digital LDO","authors":"Fan Yang, Yasu Lu, P. Mok","doi":"10.1109/APCCAS.2016.7803890","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803890","url":null,"abstract":"An analytical study of designing power stage for the emerging digital LDO is presented in this paper. Two widely adopted sizing options are discussed, namely binary and multiple-unary weighted power stage sizing. Both methods target at realizing a balanced speed and resolution of the digital LDO. The binary sizing benefits the large current step, however, in average, may render a more oscillating voltage settling. The multiple unary sizing overcomes this by a step-by-step voltage regulation, and the speed is improved if a larger step size is selected. The difference of the required clock frequency, and suggestions in designing power stage are discussed in this paper as well. This comparative analysis is further verified by simulations in a 65-nm CMOS process.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"94 1","pages":"41-42"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83920105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Simultaneous layer-aware and region-aware partitioning for 3D IC 三维集成电路的层感知和区域感知分区
2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804014
Yung-Hao Lai, Yang-Lang Chang, Jyh-Perng Fang, Jie-Hung Lee
{"title":"Simultaneous layer-aware and region-aware partitioning for 3D IC","authors":"Yung-Hao Lai, Yang-Lang Chang, Jyh-Perng Fang, Jie-Hung Lee","doi":"10.1109/APCCAS.2016.7804014","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804014","url":null,"abstract":"Through-silicon vias (TSVs) allow the stacking of dies into multilayer structures, and solve connection problems between neighboring tiers for three-dimensional (3D) integrated circuit (IC) technology. Several studies have investigated how to minimize the number of TSVs in 3D ICs, but not much focus on the total wire-length of circuit. However, with the scaling trend of CMOS technology, the power consumption due to routing resources is much higher than the other resources. In this paper, we propose a novel method of simultaneous layer-aware and region-aware partitioning (SLARAP), basing on hMetis, to reduce the number of TSVs and shorten the total wire-length of circuits simultaneously. The gigascale systems research center (GSRC) benchmarks are used as test circuits in our experiments. The experimental results show that our approach works efficiently and it can effectively reduce the total wire-length compared to iLap while considering the TSV number minimization.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"91 1","pages":"502-505"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78673789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design of low-dropout regulator using a-InGaZnO thin-film transistors 利用a-InGaZnO薄膜晶体管设计低压差稳压器
2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804025
Yongchan Kim, Hojin Lee
{"title":"Design of low-dropout regulator using a-InGaZnO thin-film transistors","authors":"Yongchan Kim, Hojin Lee","doi":"10.1109/APCCAS.2016.7804025","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804025","url":null,"abstract":"In this paper, we presented a low-dropout (LDO) regulator composed with amorphous indium-gallium-zinc-oxide thin-film transistors (a-InGaZnO TFTs) for display driving systems. Through extensive simulation works, we confirmed that the proposed LDO regulator successfully could control the output voltage levels to follow the reference input voltages, and the output voltage ripple could be suppressed below 48mV when input reference voltage was changed from 14V to 15V with 100mV fluctuation.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"15 1","pages":"546-547"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76887257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Calculating the probability of timing violation of F/F-controlled paths with timing variations
2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2016-10-01 DOI: 10.1109/APCCAS.2016.7804017
Hyun-jeong Kwon, Young Hwan Kim
{"title":"Calculating the probability of timing violation of F/F-controlled paths with timing variations","authors":"Hyun-jeong Kwon, Young Hwan Kim","doi":"10.1109/APCCAS.2016.7804017","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804017","url":null,"abstract":"We propose an analytic method to calculate the probability of timing violation of F/F-controlled paths by considering timing variations. We first characterize the timing characteristics of F/Fs and path delays using a generalized canonical delay model. The probability of setup-time violation is then calculated by considering the correlation between F/Fs and logic paths. For the calculation, we used conditional tightness probability equation which reflects the nonlinearity of the process parameters. In experiments, the proposed method exhibited the error less than 7 % with respect to Monte-Carlo (MC) simulation results. Compared to the benchmark method that does not consider the variations of the timing characteristics of F/Fs, the proposed method improved the accuracy by more than 18% on average.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"7 1","pages":"514-517"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76966718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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