A comparative analysis on binary and multiple-unary weighted power stage design for digital LDO

Abstract

An analytical study of designing power stage for the emerging digital LDO is presented in this paper. Two widely adopted sizing options are discussed, namely binary and multiple-unary weighted power stage sizing. Both methods target at realizing a balanced speed and resolution of the digital LDO. The binary sizing benefits the large current step, however, in average, may render a more oscillating voltage settling. The multiple unary sizing overcomes this by a step-by-step voltage regulation, and the speed is improved if a larger step size is selected. The difference of the required clock frequency, and suggestions in designing power stage are discussed in this paper as well. This comparative analysis is further verified by simulations in a 65-nm CMOS process.