Simultaneous layer-aware and region-aware partitioning for 3D IC

Yung-Hao Lai, Yang-Lang Chang, Jyh-Perng Fang, Jie-Hung Lee
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引用次数: 4

Abstract

Through-silicon vias (TSVs) allow the stacking of dies into multilayer structures, and solve connection problems between neighboring tiers for three-dimensional (3D) integrated circuit (IC) technology. Several studies have investigated how to minimize the number of TSVs in 3D ICs, but not much focus on the total wire-length of circuit. However, with the scaling trend of CMOS technology, the power consumption due to routing resources is much higher than the other resources. In this paper, we propose a novel method of simultaneous layer-aware and region-aware partitioning (SLARAP), basing on hMetis, to reduce the number of TSVs and shorten the total wire-length of circuits simultaneously. The gigascale systems research center (GSRC) benchmarks are used as test circuits in our experiments. The experimental results show that our approach works efficiently and it can effectively reduce the total wire-length compared to iLap while considering the TSV number minimization.
三维集成电路的层感知和区域感知分区
通过硅通孔(tsv)允许将模具堆叠成多层结构,并解决三维集成电路(IC)技术相邻层之间的连接问题。一些研究已经探讨了如何在3D集成电路中最小化tsv的数量,但很少关注电路的总线长。然而,随着CMOS技术的规模化趋势,路由资源的功耗远远高于其他资源。在本文中,我们提出了一种基于hMetis的层感知和区域感知同时划分(SLARAP)的新方法,以同时减少tsv的数量和缩短电路的总线长。在我们的实验中,使用了千兆级系统研究中心(GSRC)的基准测试电路。实验结果表明,与iLap相比,该方法可以有效地减少总线长,同时考虑到TSV数的最小化。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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