半导体技术 Pub Date : 2002-08-07 DOI: 10.1109/ASMC.2002.1001602

K. Anderson, E. Hill, A. Mitchell

{"title":"Spelunking in the data mine: on data mining as an analysis tool for the optimization of microprocessor speed","authors":"K. Anderson, E. Hill, A. Mitchell","doi":"10.1109/ASMC.2002.1001602","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001602","url":null,"abstract":"The quest for increased microprocessor speeds is inexorable... as microprocessor speeds pass two gigahertz, semiconductor manufacturers must wring all the available microprocessor speed from existing processes by any means possible. These means include designed experimentation and analysis of tightly controlled processes, many of which are approaching physical limits. Some questions an engineer must face when confronted with optimizing a 400-operation process is: At which operation to begin, and what factors in that operation influence what responses in the process? Then, after defined optimization projects have been completed: Have all the available opportunities for optimization been exhausted? One of the major products of microelectronics manufacturing is data: huge quantities of data are generated on every production lot processed through a fabrication facility. However, most of these data are observational (some would say 'happenstance') in nature, and are wrought with the problems of classical statistical analysis that experimental design procedures seek to avoid. Data Mining is loosely defined as an activity of extracting information from observational databases, wherein the goal is to discover hidden facts. One promising data mining technique is binary recursive partitioning. This technique is implemented in Classification And Regression Tree software by Salford Systems. This paper will explore the effective use of the CART/spl reg/ software tool to sift through the vast observational data generated in the production of microprocessors in the search of speed optimization opportunities. The procedures for using CART/spl reg/ to optimize microprocessor speed will be explained and demonstrated in several case studies.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81811679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Comprehensive and easy to use SEM analysis structures for BiCMOS process development 全面和易于使用的SEM分析结构，用于BiCMOS工艺开发

半导体技术 Pub Date : 2002-08-07 DOI: 10.1109/ASMC.2002.1001639

S. Leibiger

引用次数: 1

Epi resistivity profiles without wafer damage 无晶圆损坏的Epi电阻率曲线

半导体技术 Pub Date : 2002-08-07 DOI: 10.1109/ASMC.2002.1001590

K. Woolford, C. Panczyk, G. Martel

引用次数: 1

Reduce scrap: control oxide loss in SC1 减少废料:控制SC1中的氧化物损失

半导体技术 Pub Date : 2002-08-07 DOI: 10.1109/ASMC.2002.1001600

Heather Maines, M. Rathmell, L. Veldhuis

引用次数: 2

Supercritical fluid processes for semiconductor device fabrication 半导体器件制造的超临界流体工艺

半导体技术 Pub Date : 2002-08-07 DOI: 10.1109/ASMC.2002.1001636

L. Rothman, R. J. Robey, M. K. Ali, D. Mount

引用次数: 11

METRO-3D: an efficient three-dimensional wafer inspection simulator for next generation lithography METRO-3D:用于下一代光刻的高效三维晶圆检测模拟器

半导体技术 Pub Date : 2002-08-07 DOI: 10.1109/ASMC.2002.1001640

Zhengrong Zhu, A.L. Swecker, A. Strojwas

{"title":"METRO-3D: an efficient three-dimensional wafer inspection simulator for next generation lithography","authors":"Zhengrong Zhu, A.L. Swecker, A. Strojwas","doi":"10.1109/ASMC.2002.1001640","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001640","url":null,"abstract":"Wafer inspection schemes for next generation lithography (NGL) will play a key role in controlling defect mechanisms and maintaining an acceptable yield. Developing these wafer inspection schemes will require characterization and optimization of DUV wavelength illumination at high numerical apertures (greater than 0.9) to detect defects that may be a fraction of the design rule. Using wafer inspection test benches that provide the flexibility for various illumination polarizations, numerical apertures, scanning or full field schemes can be extremely costly and therefore simulation of these schemes is necessary to characterize the various detection parameters. To model defects for NGL, three-dimensional simulation tools will be required to simulate highly absorptive material in the environment of shorter wavelength illumination. Also, the simulator will be required to simulate high numerical aperture (NA) inspection schemes to capture small defects. With the development of METRO-3D, a three-dimensional simulation tool that rigorously solves the EM field on arbitrary wafer topographies, we are able to model and characterize the wafer inspection schemes for NGL. In this paper, we will present simulation results from METRO-3D for various wafer inspection schemes, including high numerical aperture schemes, on NGL topographies with highly absorptive materials.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84600590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Yield/reliability enhancement using automated minor layout modifications 使用自动化的小布局修改来提高产量和可靠性

半导体技术 Pub Date : 2002-08-07 DOI: 10.1109/ASMC.2002.1001614

G. A. Allan

引用次数: 6

Planarization yield limiters for wafer-scale 3D ICs 圆片级3D集成电路的平面化良率限制

半导体技术 Pub Date : 2002-08-07 DOI: 10.1109/ASMC.2002.1001618

M. Gupta, G. Rajagopalan, C. K. Hong, J. Lu, K. Rose, R. Gutmann

引用次数: 3

An approach for improving yield with intentional defects 一种利用故意缺陷提高良率的方法

半导体技术 Pub Date : 2002-08-07 DOI: 10.1109/ASMC.2002.1001619

Amy Engbrecht, R. Jarvis, A. Warrick