2010 IEEE International Solid-State Circuits Conference - (ISSCC)最新文献_第7页

A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS 30fJ/转换步长8b 0- 10ms /s异步SAR ADC在90nm CMOS

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433967

P. Harpe, Cui Zhou, Xiaoyang Wang, G. Dolmans, H. D. Groot

引用次数: 93

A 1V RF SoC with an 863-to-928MHz 400kb/s radio and a 32b Dual-MAC DSP core for Wireless Sensor and Body Networks 1V射频SoC, 863- 928mhz 400kb/s无线电和32b双mac DSP核心，用于无线传感器和身体网络

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433848

E. Roux, N. Scolari, B. Banerjee, C. Arm, P. Volet, D. Sigg, P. Heim, J. Perotto, F. Kaess, Nicolas Raemy, A. Vouilloz, D. Ruffieux, M. Contaldo, Frédéric Giroud, D. Séverac, M. Morgan, S. Gyger, C. Monneron, T. Le, Cesar Henzelin, V. Peiris

引用次数: 42

A timing controlled AC-DC converter for biomedical implants 一种用于生物医学植入物的定时控制AC-DC转换器

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5434021

Kim Fung Edward Lee

{"title":"A timing controlled AC-DC converter for biomedical implants","authors":"Kim Fung Edward Lee","doi":"10.1109/ISSCC.2010.5434021","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434021","url":null,"abstract":"Many biomedical implants are powered from an external magnetic source [1, 2]. The magnetic source is inductively coupled to a coil inside the implant to induce an AC voltage, which is then further rectified to a DC voltage [1]. In general, higher supply voltages are often required for analog circuits, such as stimulation circuits in neuroprosthetic applications [2, 3], and lower supply voltages are usually needed for the digital blocks [4]. Hence, the rectified DC voltage is typically kept at a higher value for the analog circuits. A linear regulator is then used to convert the rectified DC voltage to a lower supply voltage for the digital circuits, which typically have power dissipation in the range of 2 – 5mW for neuroprosthetic applications [3]. However, this approach is not very power efficient and a more efficient approach is desired due to the limited power received from the weak magnetic coupling [5]. Buck converters [6, 7] and switched-capacitor (SC) converters have higher power efficiency, especially for high load conditions. However, they may not be suitable for biomedical implants due to the limited space inside the implants, which can only accommodate a few small discrete components. Although buck converters that use a bond-wire inductor [8] or an on-chip inductor [9] are possible solutions, an alternative approach based on a direct conversion of the induced AC voltage to a regulated DC voltage is proposed. High conversion efficiency can be achieved using a single small 220nF off-chip capacitor.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"23 1","pages":"128-129"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72662928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

A 0.13µm 64Mb multi-layered conductive metal-oxide memory 一个0.13µm 64Mb多层导电金属氧化物存储器

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433945

C. Chevallier, C. Siau, S. Lim, Srivalli Namala, M. Matsuoka, B. Bateman, D. Rinerson

引用次数: 89

A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS 78mW 11.8Gb/s串行链路收发器，具有自适应RX均衡和32纳米CMOS波特率CDR

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433823

F. Spagna, Lidong Chen, M. Deshpande, Yongping Fan, D. Gambetta, Sujatha Gowder, Sitaraman V. Iyer, Rohit Kumar, P. Kwok, Renuka Krishnamurthy, Chien-chun Lin, R. Mohanavelu, Roan Nicholson, Jeff Ou, Marcus Pasquarella, K. Prasad, Hendra Rustam, Luke Tong, A. Tran, John Wu, Xuguang Zhang

{"title":"A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS","authors":"F. Spagna, Lidong Chen, M. Deshpande, Yongping Fan, D. Gambetta, Sujatha Gowder, Sitaraman V. Iyer, Rohit Kumar, P. Kwok, Renuka Krishnamurthy, Chien-chun Lin, R. Mohanavelu, Roan Nicholson, Jeff Ou, Marcus Pasquarella, K. Prasad, Hendra Rustam, Luke Tong, A. Tran, John Wu, Xuguang Zhang","doi":"10.1109/ISSCC.2010.5433823","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433823","url":null,"abstract":"The last few years have witnessed a rapid increase in serial IO data rates as well as number of IO ports in microprocessors. This trend, poses significant challenges to the serial IO design because of area and power budget limitations but, above all, by the need to achieve stringent bit error rates in the presence of interconnect constraints such as channel loss, impedance discontinuities induced by package and connectors, and crosstalk effects due to routing limitations in the package and on the motherboard. To effectively meet these challenges, the serial IO architecture has evolved to include more complex equalization schemes. Building on the previous work on a 4-tap DFE [1], this paper presents the design of a complete serial IO capable of operating up to 11.8Gb/s, and in particular, focuses on the integration of an adaptive equalizer and baud-rate CDR in the receiver of the serial IO.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"71 1","pages":"366-367"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83939161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 52

CMOS phase-locked loops for frequency synthesis 用于频率合成的CMOS锁相环

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433853

I. Galton, B. Razavi, J. Cowles, P. Kinget

引用次数: 3

A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration 10b 50MS/s 820µW SAR ADC，片上数字校准

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433965

M. Yoshioka, K. Ishikawa, T. Takayama, Sanroku Tsukamoto

{"title":"A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration","authors":"M. Yoshioka, K. Ishikawa, T. Takayama, Sanroku Tsukamoto","doi":"10.1109/ISSCC.2010.5433965","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433965","url":null,"abstract":"Rapid growth in the demand for “Green-IT” or medical applications requires power efficient ADCs. SAR ADC power scales with CMOS technology because it does not need operational amplifiers, which are getting difficult to design in deeply scaled CMOS. Recent published SAR ADCs have no static current, which improves energy efficiency [1, 2]. Split capacitor digital-to-analog converter (CDAC) is one of the best architectures for high resolution SAR ADC, but is very sensitive to the splitting capacitor because of its fractional value and parasitic. Conventional SAR ADC needs approximately 10 times faster external clock if it has no internal clock generator. However the internal SAR clock generation enables the external clock frequency to be the same as the sampling rate, but suffers from unstable operation caused by large PVT delay variation. This ADC is designed with on-chip digital calibration techniques, comparator offset calibration, CDAC linearity error calibration and internal clock frequency control to compensate for the PVT variation. The ADC is integrated in 65nm CMOS and achieved 10b at 50MS/s while consuming 820µW from a 1.0V supply.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"35 1","pages":"384-385"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88628605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 181

A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm 222mW H.264全高清解码应用处理器，40nm x512b堆叠DRAM

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433906

Yu Kikuchi, Makoto Takahashi, T. Maeda, H. Hara, H. Arakida, H. Yamamoto, Y. Hagiwara, T. Fujita, Manabu Watanabe, T. Shimazawa, Y. Ohara, T. Miyamori, M. Hamada, Y. Oowaki

{"title":"A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm","authors":"Yu Kikuchi, Makoto Takahashi, T. Maeda, H. Hara, H. Arakida, H. Yamamoto, Y. Hagiwara, T. Fujita, Manabu Watanabe, T. Shimazawa, Y. Ohara, T. Miyamori, M. Hamada, Y. Oowaki","doi":"10.1109/ISSCC.2010.5433906","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433906","url":null,"abstract":"Today's multimedia mobile devices must support a wide range of multimedia applications in addition to full high-definition (Full-HD) video processing. Conventional hardware engine approaches [1-3] cannot handle new applications that may be required once the chips are fabricated. We report an application processor with a hybrid architecture that combines a software solution with a multi-core processor [4] for various applications and a hardware solution with hardware engines for low-power and specific high-performance tasks such as Full-HD video and 3D graphics. Another issue faced in multimedia mobile devices is to achieve high memory bandwidth with low power consumption. DDR memory connections in System-in-Package (SiP) technologies need a large number of I/Os or high interface frequency at the expense of high power consumption. A Chip-on-Chip (CoC) connection using micro-bumps [5] is a power-efficient technology to achieve high memory bandwidth and low power. However, in the case of the conventional CoC technique, customized DRAM chips are necessary, because wiring between a logic chip and a DRAM chip is implemented on the metal layers in the DRAM chip. To use a DRAM chip for multiple logic LSIs, the Stacked-Chip SoC (SCS) technology used for this application processor enables rewiring at the assembly/packaging phase using minimum 5µm-pitch metal wiring on the Re-Distribution Layer (RDL). We also report an on-chip power switch with a simple structure that inhibits rush currents. The application processor has 25 power domains and controls these domains finely to optimize for various ranges of performance requirements.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"1 1","pages":"326-327"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88729777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

A 20µW neural recording tag with supply-current-modulated AFE in 0.13µm CMOS 一个20µW的神经记录标签，带有0.13µm CMOS供电电流调制AFE

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5434025

Zhiming Xiao, Chun-Ming Tang, Christopher M. Dougherty, R. Bashirullah

{"title":"A 20µW neural recording tag with supply-current-modulated AFE in 0.13µm CMOS","authors":"Zhiming Xiao, Chun-Ming Tang, Christopher M. Dougherty, R. Bashirullah","doi":"10.1109/ISSCC.2010.5434025","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434025","url":null,"abstract":"Perpetual measurement of brain activity in untethered small animal in-vivo experiments requires low power micro-systems incorporating amplification, A/D conversion, and short range wireless transmission. Overall power and communication strategies depend largely on size constraints of the implant site. For extremely small implants, these systems generally call for permanently powering the implanted recording system without the use of a battery. Such systems are primarily based on low frequency and close proximity inductive links for power and communication [1]. Alternatively, in scenarios where the implant site is less constrained, the use of small batteries can provide increased communication range [2]. In this paper, we present a 20µW neural recording tag architecture that can be either remotely powered using a transponder-reader link or operated from a small battery for increased communication range. The key features that enable this increased system flexibility are the use of a supply current modulation strategy, minimizing average power consumption of the analog-front end (AFE) and allocating larger instantaneous power levels for amplification, processing, and communication, and an uplink communication scheme based on far-field backscattering or near-field load modulation with compatibility for both battery and remotely powered systems.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"21 1","pages":"122-123"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82782640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 39

A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor 采用45nm SOI技术的32kB 2R/1W L1数据缓存，用于POWER7TM处理器

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433849

J. Pille, D. Wendel, O. Wagner, Rolf Sautter, Wolfgang Penth, Thomas Fröhnel, Stefan Büttner, O. Torreiter, Martin Eckert, Jose Paredes, David Hrusecky, David Ray, M. Canada

引用次数: 14