2010 IEEE International Solid-State Circuits Conference - (ISSCC)最新文献_第8页

Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond 完全耗尽极薄SOI主流20nm低功耗技术和超越

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5434014

Ali Khaki-Firooz, K. Cheng, B. Jagannathan, P. Kulkarni, J. Sleight, D. Shahrjerdi, Josephine B. Chang, Sungjae Lee, Junjun Li, H. Bu, R. Gauthier, B. Doris, G. Shahidi

{"title":"Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond","authors":"Ali Khaki-Firooz, K. Cheng, B. Jagannathan, P. Kulkarni, J. Sleight, D. Shahrjerdi, Josephine B. Chang, Sungjae Lee, Junjun Li, H. Bu, R. Gauthier, B. Doris, G. Shahidi","doi":"10.1109/ISSCC.2010.5434014","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434014","url":null,"abstract":"Extremely thin SOI (ETSOI) MOSFET is an attractive candidate for 22nm technology and beyond due to its excellent short channel control, low leakage current, and immunity to random dopant fluctuation [1–5]. Short channel effects are mainly controlled by channel thickness, so there is no need for aggressive scaling of the gate dielectric. Thus the gate leakage is reduced beyond what is achievable in high-k bulk technologies. Low-power operation is further enhanced by negligible GIDL current due to the undoped channel. In addition, ETSOI devices have inherently no junction leakage by the virtue of thin silicon channel. Higher gate voltage overdrive is achieved for a given supply voltage compared to bulk technologies due to smaller subthreshold slope. This enables low-VDD logic operation. Moreover, low-VDD SRAM functionality is supported by small VT- mismatch in undoped channel [5]. In conventional CMOS technologies, complete device redesign is needed if VT changes are required. In ETSOI, however, threshold voltage is tuned through gate workfunction modulation without change in the channel doping. Thus VT tuning is to a large extent decoupled from device scaling.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"2015 1","pages":"152-153"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88949828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 39

A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O 一个45nm SOI-CMOS双锁相环处理器时钟系统，用于多协议I/O

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433942

D. Fischette, A. Loke, Michael M. Oshima, B. Doyle, Roland Bakalski, Richard Joseph DeSantis, Anand Thiruvengadam, C. L. Wang, G. Talbot, E. Fang

引用次数: 24

A 90GHz-carrier 30GHz-bandwidth hybrid switching transmitter with integrated antenna 带有集成天线的90ghz载波30ghz带宽混合交换发射机

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433852

A. Arbabian, B. Afshar, Jun-Chau Chien, Shinwon Kang, Steven Callender, E. Adabi, S. D. Toso, R. Pilard, D. Gloria, A. Niknejad

引用次数: 24

A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOS 一个6.8mW 7.4Gb/s时钟转发接收器，在65nm CMOS中具有高达300MHz的抖动跟踪

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5434007

Masum Hossain, A. C. Carusone

{"title":"A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOS","authors":"Masum Hossain, A. C. Carusone","doi":"10.1109/ISSCC.2010.5434007","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434007","url":null,"abstract":"High density multilink interfaces such as QPI and HyperTransport include a dedicated link to carry a synchronous clock from the transmitter to receiver and shared by 5 – 20 data transceivers. Sub-rate clocks ameliorate jitter amplification in lossy channels. The forwarded clock must be frequency-multiplied and aligned with the data at each receiver. Per pin deskewing is done at startup [1]; the optimum deskew setting is stored and the calibration circuitry turned off during normal operation. Jitter on the forwarded clock is correlated with jitter on the data because both are generated by the same transmitter. Hence, jitter tolerance is improved by retiming the data with a clock that tracks correlated jitter on the forwarded clock [2]. However, since the delay of the data and clock paths typically differ by several UI, very high frequency jitter will appear out-of-phase at the receiver and should not be tracked. For a delay mismatch of L UI between clock and data, jitter tolerance is improved by tracking jitter up to fbit /4L [2]. If the mismatch is 5UI, at 4Gb/s and 8Gb/s the clock path jitter tracking bandwidth (JTB) should be 200MHz and 400MHz respectively. In summary, the clock path in a clock forwarded transceiver should provide flexible clock multiplication, a controlled phase shift, and a JTB adjustable over 100's of MHz to accommodate different channel losses, bit rates, and path delay mismatches.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"15 1","pages":"158-159"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89425627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Digitally assisted discontinuous conduction mode 5V/100MHz and 10V/45MHz DC-DC boost converters with integrated Schottky diodes in standard 0.13µm CMOS 数字辅助断续传导模式5V/100MHz和10V/45MHz DC-DC升压转换器集成肖特基二极管在标准0.13µm CMOS

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433983

Pengfei Li, Lin Xue, Deepak Bhatia, R. Bashirullah

{"title":"Digitally assisted discontinuous conduction mode 5V/100MHz and 10V/45MHz DC-DC boost converters with integrated Schottky diodes in standard 0.13µm CMOS","authors":"Pengfei Li, Lin Xue, Deepak Bhatia, R. Bashirullah","doi":"10.1109/ISSCC.2010.5433983","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433983","url":null,"abstract":"On-chip or on-package integration of step-up DC-DC converters in a low-voltage process can be attractive for smaller and lighter portable devices powered from single-cell batteries (i.e., NiMH, Fuel cells). To reduce the size of the off-chip components both high frequency (10 to 100s of MHz) [1, 2] and discontinuous-conduction-mode (DCM) switching have been proposed [3]. However, integration of DCM converters is challenging when the required blocking voltages across the switch and rectification stage is higher than the breakdown voltage of the standard devices. This is the case in both diode-connected MOS or CMOS controlled rectifiers for DCM boost converters [3]. Moreover, adaptive dead-time controllers are required for high-efficiency DCM operation. In this paper, we report two high-frequency DCM boost converter topologies with integrated Schottky Barrier Diodes (SBD) and a high voltage synchronous switch in a standard 0.13µm CMOS process. The SBDs are fabricated without additional processing steps to sustain ˜10V reverse voltage for high voltage operation, eliminating the need for dead-time controllers and power hungry high side drivers. The first DC-DC converter is a 100MHz digitally assisted 4-phase boost converter that delivers 240mW from a 1.2V supply with an output voltage range of 3 to 5V; and the second is a 45MHz hybrid boost converter delivering 20mW at 6-to-10V output from a 1.2V supply.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"13 1","pages":"206-207"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72726121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Westmere: A family of 32nm IA processors Westmere: 32纳米IA处理器系列

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5434033

N. Kurd, Subramani Bhamidipati, Christopher Mozak, Jeffrey L. Miller, T.M. Wilson, Mahadev Nemani, Muntaquim Chowdhury

引用次数: 93

A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization 具有二维均衡的12Gb/s 39dB无损恢复无锁dfe接收机

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5434006

M. Pozzoni, S. Erba, D. Sanzogni, M. Ganzerli, P. Viola, D. Baldi, M. Repossi, Giorgio Spelgatti, F. Svelto

引用次数: 10

A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS 完全集成2×1双频直接转换收发器，具有双模分数分压器和噪声整形TIA，适用于65nm CMOS的移动WiMAX SoC

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433966

J. Deguchi, D. Miyashita, Y. Ogasawara, Gaku Takemura, Masaomi Iwanaga, K. Sami, R. Ito, J. Wadatsumi, Y. Tsuda, S. Oda, S. Kawaguchi, N. Itoh, M. Hamada

{"title":"A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS","authors":"J. Deguchi, D. Miyashita, Y. Ogasawara, Gaku Takemura, Masaomi Iwanaga, K. Sami, R. Ito, J. Wadatsumi, Y. Tsuda, S. Oda, S. Kawaguchi, N. Itoh, M. Hamada","doi":"10.1109/ISSCC.2010.5433966","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433966","url":null,"abstract":"Mobile WiMAX complying with the IEEE 802.16e standard is one of the emerging standards and is achieving world-wide penetration. Low-cost implementation is essential and single-chip implementation is a straightforward approach. However, there are many technical challenges such as floor-planning, signal integrity and scalability of analog/RF circuits in an SoC, as well as power reduction in scaled CMOS technologies. In this work, we have designed and fabricated a fully-integrated 2RX × 1TX dual-band direct-conversion transceiver having digital interfaces for a mWiMAX SoC in a 65nm pure CMOS technology. To cope with the constraints of floor-planning while maintaining the signal integrity, inductorless local oscillator (LO) distribution using compact dual-mode fractional dividers is introduced, leading to the reduction of die area. Total noise figure of 3.8dB is achieved by a novel noise-shaping transimpedance amplifier to mitigate the flicker noise of a scaled CMOS device.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"84 1","pages":"456-457"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81063905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A 16Gb/s 1st-Tap FFE and 3-Tap DFE in 90nm CMOS 90nm CMOS 16Gb/s 1 - tap FFE和3-Tap DFE

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5434005

H. Sugita, K. Sunaga, Koichi Yamaguchi, M. Mizuno

{"title":"A 16Gb/s 1st-Tap FFE and 3-Tap DFE in 90nm CMOS","authors":"H. Sugita, K. Sunaga, Koichi Yamaguchi, M. Mizuno","doi":"10.1109/ISSCC.2010.5434005","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434005","url":null,"abstract":"Much effort has been made toward producing a high-speed multi-tap decision feedback equalizer (DFE), which would be a key component in removing inter-symbol interference (ISI) in high-speed chip-to-chip communication. A loop-unrolled approach is widely used in work toward the design of high-speed multi-tap DFEs. It eliminates the feedback operation in first post-cursor equalization [1–3], an operation that limits operational speed in conventional multi-tap DFEs. There are two problems, however, to its application to equalization of 16Gb/s signals. The first is that additional components in the feedback path, used for speculation on the basis of sampled data, increase 2nd-tap feedback delay, preventing high-speed operations. The second problem is that jitter increase in equalized waveforms prevents accurate clock timing recovery because the 1st tap ISI of the waveform is left un-equalized. In response to this situation, we have developed three techniques for achieving 16Gb/s communication: (1) an analog feedforward technique for high-speed 1st-tap ISI equalization, (2) an analog feedforward technique for jitter reduction in equalized edges, and (3) technique for employing bypass feedback and a voltage swing limiter in order to speed-up both 2ndtap and 3rd-tap equalization. We have applied these techniques to a 16Gb/s equalizer fabricated in a 90nm CMOS process, and their use helps achieve a 33% increase in operating speed over that with conventional multi-tap DFEs[3].","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"28 1","pages":"162-163"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75555464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

A 65nm CMOS low-power small-size multistandard, multiband mobile broadcasting receiver SoC 一种65nm CMOS低功耗小尺寸多标准多频段移动广播接收器SoC

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433850

M. Jeong, Bonkee Kim, Youngho Cho, Yanggyun Kim, Seyeob Kim, Heeyong Yoo, Jung-Hwan Lee, Jae Kyung Lee, Kyungsoo Jung, Jeiyoung Lee, Junghun Lee, Huikwan Yang, Gerry Taylor, Boeun Kim

引用次数: 27