E. Roux, N. Scolari, B. Banerjee, C. Arm, P. Volet, D. Sigg, P. Heim, J. Perotto, F. Kaess, Nicolas Raemy, A. Vouilloz, D. Ruffieux, M. Contaldo, Frédéric Giroud, D. Séverac, M. Morgan, S. Gyger, C. Monneron, T. Le, Cesar Henzelin, V. Peiris
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引用次数: 42
Abstract
A 150¿A/MHz DSP with two MAC/cycle instructions is integrated with a configurable 863-to-928MHz RF transceiver that yields 3.5mW in continuous reception, 2¿C per channel sampling and 40mW for 10dBm output. The SoC includes voltage converters that allow 1.0-to-1.8V or 2.7-to-3.6V primary voltage supplies. In sleep mode, it consumes 1¿A with a 32kHz crystal-based RTC running.
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