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Self- compliance unipolar resistive switching and mechanism of Cu/SiO2/TiN RRAM devices Cu/SiO2/TiN RRAM器件的自适应单极电阻开关及其机制
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243356
D. Yu, L. Liu, P. Huang, F. Zhang, B. Chen, B. Gao, Y. Hou, D. Han, Y. Wang, J. Kang, X. Zhang
{"title":"Self- compliance unipolar resistive switching and mechanism of Cu/SiO2/TiN RRAM devices","authors":"D. Yu, L. Liu, P. Huang, F. Zhang, B. Chen, B. Gao, Y. Hou, D. Han, Y. Wang, J. Kang, X. Zhang","doi":"10.1109/SNW.2012.6243356","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243356","url":null,"abstract":"CMOS compatible Cu/SiO2/TiN-based resistive random access memory (RRAM) was fabricated and investigated. Unique self-compliance unipolar resistive switching (RS) was observed, as well as good retention and uniformity of resistance states. A physical model based on formation and rupture of Cu conductive filament (CF) is proposed, considering both thermal and electrical effect, and verified by experiments.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"3 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90897349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Statistical distribution of RTS amplitudes in 20nm SOI FinFETs 20nm SOI finfet中RTS振幅的统计分布
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243347
Xingsheng Wang, A. Brown, B. Cheng, A. Asenov
{"title":"Statistical distribution of RTS amplitudes in 20nm SOI FinFETs","authors":"Xingsheng Wang, A. Brown, B. Cheng, A. Asenov","doi":"10.1109/SNW.2012.6243347","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243347","url":null,"abstract":"This abstract presents a comprehensive 3D simulation study on the impact of a single interface trapped charge in emerging 20nm gate-length FinFETs on an SOI substrate. The impact of the location of trapped charges on the Random Telegraph Signal (RTS) amplitudes is studied in detail. The RTS amplitude associated with particular trap position depends on the complex current density distribution in the Fin and is modified by `native' statistical variability sources such as metal gate granularity (MGG), line edge roughness (LER), and random discrete dopants (RDD).","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"31 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85788403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Single-electron transport through a single donor at elevated temperatures 高温下单电子通过单一供体的传递
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243293
E. Hamid, D. Moraru, T. Mizuno, M. Tabe
{"title":"Single-electron transport through a single donor at elevated temperatures","authors":"E. Hamid, D. Moraru, T. Mizuno, M. Tabe","doi":"10.1109/SNW.2012.6243293","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243293","url":null,"abstract":"We showed that, in nanoscale doped SOIFETs, new current peaks become observable as temperature is increased. For smallest 1-disk devices, a final new tunneling current peak has been observed even at T = 100 K, indicating that such patterned-channel devices are suitable for high temperature tunneling operation. Ionization energy was estimated to be about 5 times larger than for bulk Si, due to dielectric and confinement effect.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"77 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76660196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simulation study on process conditions for high-speed silicon photodetector and quantum-well structuring for increased number of wavelength discriminations 高速硅光电探测器工艺条件及增加波长分辨数的量子阱结构模拟研究
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243286
Seongjae Cho, Hyungjin Kim, Min-Chul Sun, T. Kamins, Byung-Gook Park, J. Harris
{"title":"Simulation study on process conditions for high-speed silicon photodetector and quantum-well structuring for increased number of wavelength discriminations","authors":"Seongjae Cho, Hyungjin Kim, Min-Chul Sun, T. Kamins, Byung-Gook Park, J. Harris","doi":"10.1109/SNW.2012.6243286","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243286","url":null,"abstract":"In this work, process conditions and geometric parameters for high-speed p-i-n silicon photodetector are optimized by device simulation. Efforts were made to build up criteria for device fabrication based on silicon epitaxy. For an optimized silicon photodetector, a bandwidth as wide as 80 GHz was obtained at 1 V. Furthermore, a way of increasing wavelength discriminations by introducing silicon-germanium quantum wells for multiple-wavelength signal processing is exploited.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"69 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87265779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Co-existed unipolar and bipolar resistive switching effect of HfOx-based RRAM hfox基RRAM的单极和双极电阻开关效应共存
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243333
B. Chen, B. Gao, Y. Fu, R. Liu, L. Ma, P. Huang, F. Zhang, L. Liu, X. Liu, J. Kang, G. Lian
{"title":"Co-existed unipolar and bipolar resistive switching effect of HfOx-based RRAM","authors":"B. Chen, B. Gao, Y. Fu, R. Liu, L. Ma, P. Huang, F. Zhang, L. Liu, X. Liu, J. Kang, G. Lian","doi":"10.1109/SNW.2012.6243333","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243333","url":null,"abstract":"Both unipolar and bipolar resistive switching behaviors are demonstrated and investigated in the TaTiN/HfOx/Pt structured RRAM devices. A physical model based on the recombination among the electron-depleted oxygen vacancies (VO2+) and the oxygen ions (O2-) released from the TaTiN electrode is proposed to clarify the co-existed bipolar and unipolar resistive switching effect. In the proposed physical model, Joule heating controlled O2- decomposition and electric-field controlled O2- drift dominate the unipolar and bipolar resistive switching behaviors, respectively.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"51 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90415433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Systolic architectures and applications for nanomagnet logic 纳米磁体逻辑的收缩结构与应用
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243329
M. Niemier, X. Ju, M. Becherer, G. Csaba, X. Hu, Doris Schmitt-Landsiedel, Paolo Lugli, W. Porod
{"title":"Systolic architectures and applications for nanomagnet logic","authors":"M. Niemier, X. Ju, M. Becherer, G. Csaba, X. Hu, Doris Schmitt-Landsiedel, Paolo Lugli, W. Porod","doi":"10.1109/SNW.2012.6243329","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243329","url":null,"abstract":"Most NML research has studied small magnet ensembles for interconnect or isolated gates. We discuss how NML might be used to process information, as well as suitable system architecture-to-device architecture mappings. A case study for pattern matching hardware is presented.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"106 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75297731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Fabrication and characterization of Si/SiGe quantum dots with capping gate 盖栅Si/SiGe量子点的制备与表征
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243291
T. Kodera, Y. Fukuoka, K. Takeda, T. Obata, K. Yoshida, K. Sawano, K. Uchida, Y. Shiraki, S. Tarucha, S. Oda
{"title":"Fabrication and characterization of Si/SiGe quantum dots with capping gate","authors":"T. Kodera, Y. Fukuoka, K. Takeda, T. Obata, K. Yoshida, K. Sawano, K. Uchida, Y. Shiraki, S. Tarucha, S. Oda","doi":"10.1109/SNW.2012.6243291","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243291","url":null,"abstract":"We study transport properties of quantum point contacts (QPCs) and quantum dots (QDs) with a global capping gate, fabricated on a Si/SiGe high electron mobility transistor (HEMT) wafer. By biasing the capping gate negatively, we succeed in making QPC operation point of surface Schottky gate negatively smaller and then reducing noise. We also observe Coulomb oscillations using a QD structure by suppressing charging noise with negative capping gate voltage.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"83 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82596862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Physical model for Random Telegraph Noise amplitudes and implications 随机电报噪声振幅的物理模型及其意义
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243296
R. Southwick, K. Cheung, J. Campbell, S. Drozdov, J. Ryan, J. Suehle, A. Oates
{"title":"Physical model for Random Telegraph Noise amplitudes and implications","authors":"R. Southwick, K. Cheung, J. Campbell, S. Drozdov, J. Ryan, J. Suehle, A. Oates","doi":"10.1109/SNW.2012.6243296","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243296","url":null,"abstract":"Random Telegraph Noise (RTN) has been shown to surpass random dopant fluctuations as a cause for decananometer device variability, through the measurement of a large number of ultra-scaled devices [1]. The most worrisome aspect of RTN is the tail of the amplitude distribution - the limiting cases that are rare but nevertheless wreak havoc on circuit yield and reliability. Since one cannot realistically measure enough devices to imitate a large circuit, a physics-based quantitative model is urgently needed to replace the brute force approach. Recently we introduced a physical model for RTN [2-3] but it contains a serious error. In this paper, we developed and experimentally verified a new model that provides a physical understanding of RTN amplitude. By providing a quantitative link to device parameters, it points the way to control RTN in decananometer devices.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"23 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87864768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Single Ge quantum dot placement along with self-aligned electrodes for effective management of single electron tunneling 单Ge量子点放置与自对准电极，有效地管理单电子隧穿
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243292
I. Chen, K. H. Chen, P. W. Li
{"title":"Single Ge quantum dot placement along with self-aligned electrodes for effective management of single electron tunneling","authors":"I. Chen, K. H. Chen, P. W. Li","doi":"10.1109/SNW.2012.6243292","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243292","url":null,"abstract":"We demonstrate controlled number and placement of the Ge quantum dot (QD) along with tunnel junction engineering through a self-organized approach for effective management of single electron tunneling. In this approach, a single Ge QD (~11 nm) self-aligning with nickel-silicide electrodes is realized by thermally oxidizing a SiGe nanorod bridging a 15-nm-wide nanotrench in close proximity to electrodes via a spacer bi-layer of Si3N4/SiO2. The fabricated Ge QD single electron transistor exhibits clear Coulomb staircase and Coulomb diamond behaviors at T = 120-300 K.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"72 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84511123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Nanodot-type floating gate memory with high-density nanodot array formed utilizing Listeria Dps 利用李斯特菌Dps形成具有高密度纳米点阵列的纳米点型浮栅存储器
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243352
H. Kamitake, K. Ohara, M. Uenuma, B. Zheng, Y. Ishikawa, I. Yamashita, Y. Uraoka
{"title":"Nanodot-type floating gate memory with high-density nanodot array formed utilizing Listeria Dps","authors":"H. Kamitake, K. Ohara, M. Uenuma, B. Zheng, Y. Ishikawa, I. Yamashita, Y. Uraoka","doi":"10.1109/SNW.2012.6243352","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243352","url":null,"abstract":"We formed a high-density two-dimensional nanodot array by utilizing Ti-binding Dps (TD) which is a Listeria Dps with Ti-binding peptides. A high-density nanodot array over 1012 cm-2 was formed on a SiO2 at low temperature by specific adsorption of TD. The hysteresis of the MOS capacitor with nanodot array formed utilizing TD was larger than that of the MOS capacitor fabricated utilizing ferritin. This research contributes to realizing future memory devices.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"77 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84933166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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