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Self- compliance unipolar resistive switching and mechanism of Cu/SiO2/TiN RRAM devices Cu/SiO2/TiN RRAM器件的自适应单极电阻开关及其机制
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243356
D. Yu, L. Liu, P. Huang, F. Zhang, B. Chen, B. Gao, Y. Hou, D. Han, Y. Wang, J. Kang, X. Zhang
{"title":"Self- compliance unipolar resistive switching and mechanism of Cu/SiO2/TiN RRAM devices","authors":"D. Yu, L. Liu, P. Huang, F. Zhang, B. Chen, B. Gao, Y. Hou, D. Han, Y. Wang, J. Kang, X. Zhang","doi":"10.1109/SNW.2012.6243356","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243356","url":null,"abstract":"CMOS compatible Cu/SiO2/TiN-based resistive random access memory (RRAM) was fabricated and investigated. Unique self-compliance unipolar resistive switching (RS) was observed, as well as good retention and uniformity of resistance states. A physical model based on formation and rupture of Cu conductive filament (CF) is proposed, considering both thermal and electrical effect, and verified by experiments.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90897349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Statistical distribution of RTS amplitudes in 20nm SOI FinFETs 20nm SOI finfet中RTS振幅的统计分布
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243347
Xingsheng Wang, A. Brown, B. Cheng, A. Asenov
{"title":"Statistical distribution of RTS amplitudes in 20nm SOI FinFETs","authors":"Xingsheng Wang, A. Brown, B. Cheng, A. Asenov","doi":"10.1109/SNW.2012.6243347","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243347","url":null,"abstract":"This abstract presents a comprehensive 3D simulation study on the impact of a single interface trapped charge in emerging 20nm gate-length FinFETs on an SOI substrate. The impact of the location of trapped charges on the Random Telegraph Signal (RTS) amplitudes is studied in detail. The RTS amplitude associated with particular trap position depends on the complex current density distribution in the Fin and is modified by `native' statistical variability sources such as metal gate granularity (MGG), line edge roughness (LER), and random discrete dopants (RDD).","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85788403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Single-electron transport through a single donor at elevated temperatures 高温下单电子通过单一供体的传递
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243293
E. Hamid, D. Moraru, T. Mizuno, M. Tabe
{"title":"Single-electron transport through a single donor at elevated temperatures","authors":"E. Hamid, D. Moraru, T. Mizuno, M. Tabe","doi":"10.1109/SNW.2012.6243293","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243293","url":null,"abstract":"We showed that, in nanoscale doped SOIFETs, new current peaks become observable as temperature is increased. For smallest 1-disk devices, a final new tunneling current peak has been observed even at T = 100 K, indicating that such patterned-channel devices are suitable for high temperature tunneling operation. Ionization energy was estimated to be about 5 times larger than for bulk Si, due to dielectric and confinement effect.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76660196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simulation study on process conditions for high-speed silicon photodetector and quantum-well structuring for increased number of wavelength discriminations 高速硅光电探测器工艺条件及增加波长分辨数的量子阱结构模拟研究
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243286
Seongjae Cho, Hyungjin Kim, Min-Chul Sun, T. Kamins, Byung-Gook Park, J. Harris
{"title":"Simulation study on process conditions for high-speed silicon photodetector and quantum-well structuring for increased number of wavelength discriminations","authors":"Seongjae Cho, Hyungjin Kim, Min-Chul Sun, T. Kamins, Byung-Gook Park, J. Harris","doi":"10.1109/SNW.2012.6243286","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243286","url":null,"abstract":"In this work, process conditions and geometric parameters for high-speed p-i-n silicon photodetector are optimized by device simulation. Efforts were made to build up criteria for device fabrication based on silicon epitaxy. For an optimized silicon photodetector, a bandwidth as wide as 80 GHz was obtained at 1 V. Furthermore, a way of increasing wavelength discriminations by introducing silicon-germanium quantum wells for multiple-wavelength signal processing is exploited.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87265779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Co-existed unipolar and bipolar resistive switching effect of HfOx-based RRAM hfox基RRAM的单极和双极电阻开关效应共存
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243333
B. Chen, B. Gao, Y. Fu, R. Liu, L. Ma, P. Huang, F. Zhang, L. Liu, X. Liu, J. Kang, G. Lian
{"title":"Co-existed unipolar and bipolar resistive switching effect of HfOx-based RRAM","authors":"B. Chen, B. Gao, Y. Fu, R. Liu, L. Ma, P. Huang, F. Zhang, L. Liu, X. Liu, J. Kang, G. Lian","doi":"10.1109/SNW.2012.6243333","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243333","url":null,"abstract":"Both unipolar and bipolar resistive switching behaviors are demonstrated and investigated in the TaTiN/HfOx/Pt structured RRAM devices. A physical model based on the recombination among the electron-depleted oxygen vacancies (VO2+) and the oxygen ions (O2-) released from the TaTiN electrode is proposed to clarify the co-existed bipolar and unipolar resistive switching effect. In the proposed physical model, Joule heating controlled O2- decomposition and electric-field controlled O2- drift dominate the unipolar and bipolar resistive switching behaviors, respectively.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90415433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Analysis of static noise margin and power-gating efficiency of a new nonvolatile SRAM cell using pseudo-spin-MOSFETs 基于伪自旋mosfet的新型非易失SRAM单元的静态噪声裕度和功率门控效率分析
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243330
Y. Shuto, S. Yamamoto, S. Sugahara
{"title":"Analysis of static noise margin and power-gating efficiency of a new nonvolatile SRAM cell using pseudo-spin-MOSFETs","authors":"Y. Shuto, S. Yamamoto, S. Sugahara","doi":"10.1109/SNW.2012.6243330","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243330","url":null,"abstract":"Static noise margins (SNMs) and power-gating efficiency were computationally analyzed for our proposed nonvolatile SRAM (NV-SRAM) cell based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque MTJs (STT-MTJs). The NV-SRAM cell has the same SNMs as an optimized 6T-SRAM cell. SNMs for other recently-proposed NV-SRAM cells using STT-MTJs were also evaluated, and we showed that their SNMs were deteriorated owing to the effect of the constituent STT-MTJs. Break-even time (BET) and power efficiency were analyzed for the NV-SRAM cell using PS-MOSFETs. The BET can be successfully minimized by controlling the bias of the cell. The average power dissipation can be effectively reduced by power-gating (PG) executions, and the further reduction is made possible by introducing a sleep mode.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89087947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Optoelectrical lifetime evaluation of single holes in SOI MOSFET SOI MOSFET单孔光电寿命评估
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243297
Wei Du, D. Putranto, H. Satoh, A. Ono, P. Priambodo, D. Hartanto, H. Inokawa
{"title":"Optoelectrical lifetime evaluation of single holes in SOI MOSFET","authors":"Wei Du, D. Putranto, H. Satoh, A. Ono, P. Priambodo, D. Hartanto, H. Inokawa","doi":"10.1109/SNW.2012.6243297","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243297","url":null,"abstract":"Optoelectrical method to evaluate the lifetime of single holes in SOI MOSFET is presented, in which the device is illuminated with a continuous light and the histograms of the digitized drain current is analyzed. It was found that smaller number of holes and the higher transverse electric field greatly enhance the hole lifetime.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90876587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fabrication and characterization of Si/SiGe quantum dots with capping gate 盖栅Si/SiGe量子点的制备与表征
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243291
T. Kodera, Y. Fukuoka, K. Takeda, T. Obata, K. Yoshida, K. Sawano, K. Uchida, Y. Shiraki, S. Tarucha, S. Oda
{"title":"Fabrication and characterization of Si/SiGe quantum dots with capping gate","authors":"T. Kodera, Y. Fukuoka, K. Takeda, T. Obata, K. Yoshida, K. Sawano, K. Uchida, Y. Shiraki, S. Tarucha, S. Oda","doi":"10.1109/SNW.2012.6243291","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243291","url":null,"abstract":"We study transport properties of quantum point contacts (QPCs) and quantum dots (QDs) with a global capping gate, fabricated on a Si/SiGe high electron mobility transistor (HEMT) wafer. By biasing the capping gate negatively, we succeed in making QPC operation point of surface Schottky gate negatively smaller and then reducing noise. We also observe Coulomb oscillations using a QD structure by suppressing charging noise with negative capping gate voltage.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82596862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Silicon microfabrication technologies for THz applications 太赫兹应用的硅微加工技术
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243285
C. Jung-Kubiak, J. Gill, T. Reck, C. Lee, J. Siles, G. Chattopadhyay, R. Lin, K. Cooper, I. Mehdi
{"title":"Silicon microfabrication technologies for THz applications","authors":"C. Jung-Kubiak, J. Gill, T. Reck, C. Lee, J. Siles, G. Chattopadhyay, R. Lin, K. Cooper, I. Mehdi","doi":"10.1109/SNW.2012.6243285","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243285","url":null,"abstract":"Silicon micromachining technology is naturally suited for making THz components, where precision and accuracy are essentials. We report here the development of robust micromachining techniques to enable novel active and passive components in the submillimeter-wave region. These features will enable large format submillimeter-wave heterodyne arrays and 3-D integration in the THz region, where fabricating circuits and structures becomes difficult with conventional machining.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80946270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Nanodot-type floating gate memory with high-density nanodot array formed utilizing Listeria Dps 利用李斯特菌Dps形成具有高密度纳米点阵列的纳米点型浮栅存储器
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243352
H. Kamitake, K. Ohara, M. Uenuma, B. Zheng, Y. Ishikawa, I. Yamashita, Y. Uraoka
{"title":"Nanodot-type floating gate memory with high-density nanodot array formed utilizing Listeria Dps","authors":"H. Kamitake, K. Ohara, M. Uenuma, B. Zheng, Y. Ishikawa, I. Yamashita, Y. Uraoka","doi":"10.1109/SNW.2012.6243352","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243352","url":null,"abstract":"We formed a high-density two-dimensional nanodot array by utilizing Ti-binding Dps (TD) which is a Listeria Dps with Ti-binding peptides. A high-density nanodot array over 1012 cm-2 was formed on a SiO2 at low temperature by specific adsorption of TD. The hysteresis of the MOS capacitor with nanodot array formed utilizing TD was larger than that of the MOS capacitor fabricated utilizing ferritin. This research contributes to realizing future memory devices.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84933166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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