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A +30.5 dBm CMOS Doherty power amplifier with reliability enhancement technique 采用可靠性增强技术的+30.5 dBm CMOS Doherty功率放大器
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243798
Kohei Onizuka, S. Saigusa, S. Otaka
{"title":"A +30.5 dBm CMOS Doherty power amplifier with reliability enhancement technique","authors":"Kohei Onizuka, S. Saigusa, S. Otaka","doi":"10.1109/VLSIC.2012.6243798","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243798","url":null,"abstract":"A watt-level, fully integrated 1:1 Doherty power amplifier for 2.4 GHz band is demonstrated in 65 nm CMOS. Both high peak output power of +30.5 dBm and high PAE of 23% at 6 dB power back-off are achieved by the proposed compact output network. A newly introduced reliability enhancement technique for sub-PA prolongs time to failure by up to 75% as well. The PA satisfies IEEE 802.11b and 11g spectrum masks at output power levels of 25.5 and 21.5 dBm respectively, from supply voltage of 3.3 V.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"26 1","pages":"78-79"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80423768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
An 85dB SFDR 67dB SNDR 8OSR 240MS/s ΔΣ ADC with nonlinear memory error calibration 85dB SFDR 67dB SNDR 8OSR 240MS/s ΔΣ非线性记忆误差校准ADC
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243841
Seung-Chul Lee, Brian Elies, Y. Chiu
{"title":"An 85dB SFDR 67dB SNDR 8OSR 240MS/s ΔΣ ADC with nonlinear memory error calibration","authors":"Seung-Chul Lee, Brian Elies, Y. Chiu","doi":"10.1109/VLSIC.2012.6243841","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243841","url":null,"abstract":"A 1-0 MASH ΔΣ ADC demonstrates a digital calibration technique treating both amplifier distortion and capacitor mismatch. The output-referred error analysis accurately models a nonlinear modulator. The identification of multiple error parameters is accomplished by correlating various moments of the ADC output with a one-bit pseudorandom noise (PN). The prototype ADC employing 29dB gain amplifiers measures 85dB SFDR and 67dB SNDR for a -1dBFS (1.1Vpp) 5MHz sinusoidal input at 240MS/s. The core ADC consumes 37mW from a 1.25V supply and occupies 0.28mm2 in a 65nm CMOS low-leakage digital process, in which the transistor threshold voltages are around 0.5V.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"16 1","pages":"164-165"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79655523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A UWB IR timed-array radar using time-shifted direct-sampling architecture 采用时移直接采样结构的超宽带红外时阵雷达
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243786
C. Lai, K. Tan, L. Yu, Yen-Ju Chen, Jun-Wei Huang, Shr-Chau Lai, Feng-Hsu Chung, Chia-Fung Yen, Jen-Ming Wu, Po-Chiun Huang, Keh-Jeng Chang, Shi-Yu Huang, Ta-Shun Chu
{"title":"A UWB IR timed-array radar using time-shifted direct-sampling architecture","authors":"C. Lai, K. Tan, L. Yu, Yen-Ju Chen, Jun-Wei Huang, Shr-Chau Lai, Feng-Hsu Chung, Chia-Fung Yen, Jen-Ming Wu, Po-Chiun Huang, Keh-Jeng Chang, Shi-Yu Huang, Ta-Shun Chu","doi":"10.1109/VLSIC.2012.6243786","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243786","url":null,"abstract":"A UWB impulse radio (IR) timed-array radar using time-shifted direct-sampling architecture is presented. The transmitter array can generate and send a variety of 10GS/s pulses towards targets. The receiver array samples the reflected signal in RF domain directly by time interleaved sampling with equivalent sampling rate of 20 GS/s. The radar system can determine time of arrival (TOA) and direction of arrival (DOA) through time-shifted sampling edges which are generated by on-chip digital-to-time converters (DTC). The proposed architecture has range and azimuth resolution of 0.75 cm and 3 degree respectively. This prototype is implemented in a 0.18μm CMOS technology.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"20 1","pages":"54-55"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82634219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An 8-PPM, 45 pJ/bit UWB transmitter with reduced number of PA elements 一个8 ppm, 45 pJ/bit的UWB发射机，减少了PA元件的数量
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243777
V. Majidzadeh, A. Schmid, Y. Leblebici, J. Rabaey
{"title":"An 8-PPM, 45 pJ/bit UWB transmitter with reduced number of PA elements","authors":"V. Majidzadeh, A. Schmid, Y. Leblebici, J. Rabaey","doi":"10.1109/VLSIC.2012.6243777","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243777","url":null,"abstract":"A pulsed UWB transmitter (Tx) using finite impulse response synthesis of the raised-cosine pulse is presented. Symmetric pulse combining technique is proposed to reduce the number of power amplifier elements by half. A novel all-digital delay locked loop (AD-DLL) serves as an 8-array pulse position modulator (PPM) for aggressive duty-cycling of the Tx. The chip is fabricated with 90nm CMOS technology and consumes 540 μW from 1 V power supply resulting in 45 pJ/bit energy efficiency with -26 dBm of output power.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"42 1","pages":"36-37"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86518893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS 采用模拟FE的25gb /s 2.2 w光模块，可承受电源噪声和冗余数据格式转换，采用65nm CMOS
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243812
T. Takemoto, H. Yamashita, Takehito Kamimura, F. Yuki, N. Masuda, H. Toyoda, N. Chujo, K. Kogo, Yong Lee, S. Tsuji, S. Nishimura
{"title":"A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS","authors":"T. Takemoto, H. Yamashita, Takehito Kamimura, F. Yuki, N. Masuda, H. Toyoda, N. Chujo, K. Kogo, Yong Lee, S. Tsuji, S. Nishimura","doi":"10.1109/VLSIC.2012.6243812","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243812","url":null,"abstract":"A one-chip transceiver was developed for optical backplanes by integrating an analog FE with data format conversion in 65-nm CMOS. 10×6.25Gb/s electrical signals were converted to 4×25Gb/s optical signals with 25% redundancy to improve resilience against possible LD failure. To alleviate degradation of the optical link due to power-supply variations, a TIA with a noise canceller and a fully differential LDD are proposed. The noise canceller decreases power-supply variations by 98%. Total power consumption was only 2.2W.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"58 1","pages":"106-107"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83961523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS 2.4GHz WLAN收发器，完全集成高线性1.8V 28.4dBm PA, 34dBm T/R开关，240MS/s DAC, 320MS/s ADC和DPLL，采用32nm SoC CMOS
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243797
Yulin Tan, J. Duster, C. Fu, E. Alpman, A. Balankutty, Chun C. Lee, A. Ravi, S. Pellerano, K. Chandrashekar, Hyung Seok Kim, B. Carlton, Satoshi Suzuki, M. Shafi, Y. Palaskas, H. Lakdawala
{"title":"A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS","authors":"Yulin Tan, J. Duster, C. Fu, E. Alpman, A. Balankutty, Chun C. Lee, A. Ravi, S. Pellerano, K. Chandrashekar, Hyung Seok Kim, B. Carlton, Satoshi Suzuki, M. Shafi, Y. Palaskas, H. Lakdawala","doi":"10.1109/VLSIC.2012.6243797","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243797","url":null,"abstract":"A 2.4GHz WLAN transceiver is presented with a fully-integrated highly-linear 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC and 320MS/s ADC (high OSR for relaxed filtering), DPLL and fractional LOG, in 32nm CMOS. For 802.11g 54Mbps, without linearization the TX delivers 19.8dBm at 12.5% efficiency (PA 21.6dBm/19.7% PAE) for -25dB EVM and mask-compliant 22.8dBm/18.5%, while the RX achieves 4.8dB NF, -69dBm sensitivity, and -8dBm IIP3.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"34 1","pages":"76-77"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81169130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 3-stage Pseudo Single-phase Flip-flop family 一个3级伪单相触发器系列
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243845
H. Partovi, A. Yeung, L. Ravezzi, M. Horowitz
{"title":"A 3-stage Pseudo Single-phase Flip-flop family","authors":"H. Partovi, A. Yeung, L. Ravezzi, M. Horowitz","doi":"10.1109/VLSIC.2012.6243845","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243845","url":null,"abstract":"This paper presents an energy-efficient 3-stage Pseudo Single-phase family of Flip-flops (PSPFF) targeted for use in a 3GHz microprocessor in a 40nm, 0.9V CMOS technology. With latencies in line with the fast pulsed-latch and an average switching energy comparable to the master-slave flip-flop, PSPFF achieves an energy-delay product (EDP) which is 42% and 24% lower than the pulsed-latch and the master-slave flip-flop respectively. Measurement results confirm an improvement of at least 300MHz in operating frequency when using the PSPFF in place of the master-slave flip-flop.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"5 1","pages":"172-173"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87309970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS 32nm CMOS 3.1mW/Gbps 30Gbps四分之一速率三推测15分路SC-DFE RX数据路径
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243810
T. Toifl, M. Ruegg, Rajesh Inti, C. Menolfi, M. Braendli, M. Kossel, P. Buchmann, P. Francese, T. Morf
{"title":"A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS","authors":"T. Toifl, M. Ruegg, Rajesh Inti, C. Menolfi, M. Braendli, M. Kossel, P. Buchmann, P. Francese, T. Morf","doi":"10.1109/VLSIC.2012.6243810","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243810","url":null,"abstract":"This paper describes a low-power implementation of a receiver data path, consisting of the RX termination with ESD, continuous-time linear equalizer (CTLE), and a 15-tap decision feedback equalizer (DFE) running at quarter rate. While the first 3 DFE taps are implemented by speculation, the latter 12 taps use a switched-cap (SC-DFE) approach. The circuit was produced in 32nm SOI-CMOS, and was measured to receive 30Gb/s PRBS31 data at <;10-12 BER over a 36dB loss channel with an energy efficiency of 3.1mW/Gbps.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"6 1","pages":"102-103"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79720404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A 4.5-mW 8-b 750-MS/s 2-b/step asynchronous subranged SAR ADC in 28-nm CMOS technology 采用28纳米CMOS技术的4.5 mw 8-b 750-MS/s 2-b/步异步分段SAR ADC
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243803
Yuanching Lien
{"title":"A 4.5-mW 8-b 750-MS/s 2-b/step asynchronous subranged SAR ADC in 28-nm CMOS technology","authors":"Yuanching Lien","doi":"10.1109/VLSIC.2012.6243803","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243803","url":null,"abstract":"A 8-b 2-b/step asynchronous subranged SAR ADC is presented. It incorporates subranging technique to obtain fast reference settling for MSB conversion. The capacitive interpolation reduces number of NMOS switches and lowers matching requirement of a resistive DAC. The proposed timing scheme avoids the need of specific duty cycle of external clock for defining sampling period in a conventional asynchronous SAR ADC. Operating at 750 MS/s, this ADC consumes 4.5 mW from 1-V supply, achieves ENOB of 7.2 and FOM of 41 fJ/conversion-step. It is fabricated in 28-nm CMOS technology and occupies an active area of 0.004 mm2.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"12 1","pages":"88-89"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75519804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 74
Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment 设计一个2.5 ghz、3ps抖动、8个锁相周期、全数字锁相周期相位调节的延迟锁相环
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243852
Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh, J. Sheu
{"title":"Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment","authors":"Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh, J. Sheu","doi":"10.1109/VLSIC.2012.6243852","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243852","url":null,"abstract":"This paper describes the design of a multi-GHz ADDLL. HDSC-based coarse-fine architecture is adopted to achieve low power and to avoid harmonic locking at large operating frequency ranges. A new resettable coarse delay line and an asynchronous binary-search design are proposed to achieve fast coarse locking and fine locking, respectively. A novel maintenance operation is also proposed to allow phase adjustments to be performed during each cycle to effectively suppress the jitter. The measurement results show that the designed 1.0-V, 55-nm ADDLL has a peak-to-peak jitter of 3 ps and a locking time of 8 cycles when operated at 2.5 GHz with a power dissipation of only 1.96 mW.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"4 1","pages":"186-187"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73453337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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