An 85dB SFDR 67dB SNDR 8OSR 240MS/s ΔΣ ADC with nonlinear memory error calibration

Abstract

A 1-0 MASH ΔΣ ADC demonstrates a digital calibration technique treating both amplifier distortion and capacitor mismatch. The output-referred error analysis accurately models a nonlinear modulator. The identification of multiple error parameters is accomplished by correlating various moments of the ADC output with a one-bit pseudorandom noise (PN). The prototype ADC employing 29dB gain amplifiers measures 85dB SFDR and 67dB SNDR for a -1dBFS (1.1Vpp) 5MHz sinusoidal input at 240MS/s. The core ADC consumes 37mW from a 1.25V supply and occupies 0.28mm2 in a 65nm CMOS low-leakage digital process, in which the transistor threshold voltages are around 0.5V.