A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243810

T. Toifl, M. Ruegg, Rajesh Inti, C. Menolfi, M. Braendli, M. Kossel, P. Buchmann, P. Francese, T. Morf

引用次数: 20

Abstract

This paper describes a low-power implementation of a receiver data path, consisting of the RX termination with ESD, continuous-time linear equalizer (CTLE), and a 15-tap decision feedback equalizer (DFE) running at quarter rate. While the first 3 DFE taps are implemented by speculation, the latter 12 taps use a switched-cap (SC-DFE) approach. The circuit was produced in 32nm SOI-CMOS, and was measured to receive 30Gb/s PRBS31 data at <;10-12 BER over a 36dB loss channel with an energy efficiency of 3.1mW/Gbps.

查看原文本刊更多论文

32nm CMOS 3.1mW/Gbps 30Gbps四分之一速率三推测15分路SC-DFE RX数据路径

本文描述了一个接收器数据路径的低功耗实现，包括带有ESD的RX终端、连续时间线性均衡器(CTLE)和一个以四分之一速率运行的15分路决策反馈均衡器(DFE)。虽然前3个DFE抽头是通过推测实现的，但后12个抽头使用开关盖(SC-DFE)方法。该电路采用32nm SOI-CMOS制作，在36dB损耗通道上以< 10-12 BER接收30Gb/s PRBS31数据，能量效率为3.1mW/Gbps。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2012 Symposium on VLSI Circuits (VLSIC)

自引率

0.00%

发文量