A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243797

Yulin Tan, J. Duster, C. Fu, E. Alpman, A. Balankutty, Chun C. Lee, A. Ravi, S. Pellerano, K. Chandrashekar, Hyung Seok Kim, B. Carlton, Satoshi Suzuki, M. Shafi, Y. Palaskas, H. Lakdawala

引用次数: 9

Abstract

A 2.4GHz WLAN transceiver is presented with a fully-integrated highly-linear 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC and 320MS/s ADC (high OSR for relaxed filtering), DPLL and fractional LOG, in 32nm CMOS. For 802.11g 54Mbps, without linearization the TX delivers 19.8dBm at 12.5% efficiency (PA 21.6dBm/19.7% PAE) for -25dB EVM and mask-compliant 22.8dBm/18.5%, while the RX achieves 4.8dB NF, -69dBm sensitivity, and -8dBm IIP3.

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2.4GHz WLAN收发器，完全集成高线性1.8V 28.4dBm PA, 34dBm T/R开关，240MS/s DAC, 320MS/s ADC和DPLL，采用32nm SoC CMOS

一款2.4GHz无线局域网收发器采用32nm CMOS，具有完全集成的高线性28.4dBm PA, 34dBm T/R开关，240MS/s DAC和320MS/s ADC(放松滤波的高OSR)， DPLL和分数LOG。对于802.11g 54Mbps，无需线性化，在-25dB EVM和-69dBm掩模兼容的情况下，TX以12.5%的效率输出19.8dBm (PA 21.6dBm/19.7% PAE)，而RX实现4.8dB NF， -69dBm灵敏度和-8dBm IIP3。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2012 Symposium on VLSI Circuits (VLSIC)

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