2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献_第8页

AVF-driven parity optimization for MBU protection of in-core memory arrays avf驱动的核心存储器阵列MBU保护奇偶优化

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.301

M. Maniatakos, M. Michael, Y. Makris

{"title":"AVF-driven parity optimization for MBU protection of in-core memory arrays","authors":"M. Maniatakos, M. Michael, Y. Makris","doi":"10.7873/DATE.2013.301","DOIUrl":"https://doi.org/10.7873/DATE.2013.301","url":null,"abstract":"We propose an AVF-driven parity selection method for protecting modern microprocessor in-core memory arrays against MBUs. As MBUs constitute more than 50% of the upsets in latest technologies, error correcting codes or physical interleaving are typically employed to effectively protect out-of-core memory structures, such as caches. However, such methods are not applicable to high-performance in-core arrays, due to computational complexity, high delay and area overhead. To this end, we revisit parity as an effective mechanism to detect errors and we resort to pipeline flushing and checkpointing for correction. We demonstrate that optimal parity tree construction for MBU detection is a computationally complex problem, which we then formulate as an integer-linear-program (ILP). Experimental results on Alpha 21264 and Intel P6 in-core memory arrays demonstrate that optimal parity tree selection can achieve great vulnerability reduction, even when a small number of bits are added to the parity trees, compared to simple heuristics. Furthermore, the ILP formulation allows us to find better solutions by effectively exploring the solution space in the presence of multiple parity trees; results show that the presence of 2 parity trees offers a vulnerability reduction of more than 50% over a single parity tree.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"258263 1","pages":"1480-1485"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77537818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Efficient importance sampling for high-sigma yield analysis with adaptive online surrogate modeling 基于自适应在线代理模型的高效重要抽样高西格玛产量分析

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.267

Jian Yao, Zuochang Ye, Yan Wang

引用次数: 15

Future of GPGPU micro-architectural parameters GPGPU微架构参数的未来

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.089

C. Nugteren, Gert-Jan van den Braak, H. Corporaal

引用次数: 6

Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write VMIN 利用灵敏度分析快速，准确地估计SRAM动态写入VMIN

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.364

James Boley, V. Chandra, R. Aitken, B. Calhoun

引用次数: 11

Efficient and scalable OpenMP-based system-level design 高效和可扩展的基于openmp的系统级设计

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.206

A. Cilardo, L. Gallo, A. Mazzeo, N. Mazzocca

引用次数: 34

Capital cost-aware design and partial shading-aware architecture optimization of a reconfigurable photovoltaic system 可重构光伏系统的资本成本感知设计和部分遮阳感知架构优化

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.191

Yanzhi Wang, X. Lin, Massoud Pedram, Jaemin Kim, N. Chang

{"title":"Capital cost-aware design and partial shading-aware architecture optimization of a reconfigurable photovoltaic system","authors":"Yanzhi Wang, X. Lin, Massoud Pedram, Jaemin Kim, N. Chang","doi":"10.7873/DATE.2013.191","DOIUrl":"https://doi.org/10.7873/DATE.2013.191","url":null,"abstract":"Photovoltaic (PV) systems are often subject to partial shading that significantly degrades the output power of the whole systems. Reconfiguration methods have been proposed to adaptively change the PV panel configuration according to the current partial shading pattern. The reconfigurable PV panel architecture integrates every PV cell with three programmable switches to facilitate the PV panel reconfiguration. The additional switches, however, increase the capital cost of the PV system. In this paper, we group a number of PV cells into a PV macro-cell, and the PV panel reconfiguration only changes the connections between adjacent PV macro-cells. The size and internal structure (i.e., the series-parallel connection of PV cells) of all PV macro-cells are the same and will not be changed after PV system installation in the field. Determining the optimal size of the PV macro-cell is the result of a trade-off between the decreased PV system capital cost and enhanced PV system performance. A larger PV macro-cell reduces the cost overhead whereas a smaller PV macro-cell achieves better performance. In this paper, we set out to calculate the optimal size of the PV macro-cells such that the maximum system performance can be achieved subject to an overall system cost limitation. This “design” problem is solved using an efficient search algorithm. In addition, we provide for in-field reconfigurability of the PV panel by enabling formation of series-connected groups of parallel-connected macro-cells. We ensure maximum output power for the PV system in response to any incurring partial shading pattern. This “architecture optimization” problem is solved using dynamic programming.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"45 1","pages":"909-912"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73753969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Priority assignment for event-triggered systems using mathematical programming 使用数学规划的事件触发系统的优先级分配

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.5555/2485288.2485524

M. Lukasiewycz, S. Steinhorst, S. Chakraborty

{"title":"Priority assignment for event-triggered systems using mathematical programming","authors":"M. Lukasiewycz, S. Steinhorst, S. Chakraborty","doi":"10.5555/2485288.2485524","DOIUrl":"https://doi.org/10.5555/2485288.2485524","url":null,"abstract":"This paper presents a methodology based on mathematical programming for the priority assignment of processes and messages in event-triggered systems with tight end-to-end real-time deadlines. For this purpose, the problem is converted into a Quadratically Constrained Quadratic Program (QCQP) and addressed with a state-of-the-art solver. The formulation includes preemptive as well as non-preemptive schedulers and avoids cyclic dependencies that may lead to intractable real-time analysis problems. For problems with stringent real-time requirements, the proposed mathematical programming method is capable of finding a feasible solution efficiently where other approaches suffer from a poor scalability. In case there exists no feasible solution, an algorithm is presented that uses the proposed method to find a minimal reason for the infeasibility which may be used as a feedback to the designer. To give evidence of the scalability of the proposed method and in order to show the clear benefit over existing approaches, a set of synthetic test cases is evaluated. Finally, a large realistic case study is introduced and solved, showing the applicability of the proposed method in the automotive domain.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"27 1","pages":"982-987"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73344511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

System-level modeling of energy in TLM for early validation of power and thermal management TLM中的系统级能量建模，用于功率和热管理的早期验证

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.327

Tayeb Bouhadiba, M. Moy, F. Maraninchi

{"title":"System-level modeling of energy in TLM for early validation of power and thermal management","authors":"Tayeb Bouhadiba, M. Moy, F. Maraninchi","doi":"10.7873/DATE.2013.327","DOIUrl":"https://doi.org/10.7873/DATE.2013.327","url":null,"abstract":"Modern systems-on-a-chip are equipped with power architectures, allowing to control the consumption of individual components or subsystems. These mechanisms are controlled by a power-management policy often implemented in the embedded software, with hardware support. Today's circuits have an important static power consumption, whose low-power design require techniques like DVFS or power-gating. A correct and efficient management of these mechanisms is therefore becoming non-trivial. Validating the effect of the power management policy needs to be done very early in the design cycle, as part of the architecture exploration activity. High-level models of the hardware must be annotated with consumption information. Temperature must also be taken into account since leakage current increases exponentially with it. Existing annotation techniques applied to loosely-timed or temporally-decoupled models would create bad simulation artifacts on the temperature profile (e.g. unrealistic peaks). This paper addresses the instrumentation of a timed transaction-level model of the hardware with information on the power consumption of the individual components. It can cope not only with power-state models, but also with Joule-per-bit traffic models, and avoids simulation artifacts when used in a functional/power/temperature co-simulation.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"16 1","pages":"1609-1614"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73667352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 37

Comprehensive analysis of software countermeasures against fault attacks 针对故障攻击的软件对策综合分析

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.092

Nikolaus Theißing, D. Merli, M. Smola, F. Stumpf, G. Sigl

引用次数: 16

SmartCap: User experience-oriented power adaptation for smartphone's application processor SmartCap:面向用户体验的智能手机应用处理器电源适配

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.026

Xueliang Li, Guihai Yan, Yinhe Han, Xiaowei Li

引用次数: 28