2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献_第9页

GPU-friendly floating random walk algorithm for capacitance extraction of VLSI interconnects 基于gpu友好的VLSI互连电容提取浮动随机游走算法

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.336

Kuangya Zhai, Wenjian Yu, H. Zhuang

引用次数: 25

Is split manufacturing secure? 拆分制造安全吗?

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.261

Jeyavijayan Rajendran, O. Sinanoglu, R. Karri

{"title":"Is split manufacturing secure?","authors":"Jeyavijayan Rajendran, O. Sinanoglu, R. Karri","doi":"10.7873/DATE.2013.261","DOIUrl":"https://doi.org/10.7873/DATE.2013.261","url":null,"abstract":"Split manufacturing of integrated circuits (IC) is being investigated as a way to simultaneously alleviate the cost of owning a trusted foundry and eliminate the security risks associated with outsourcing IC fabrication. In split manufacturing, a design house (with a low-end, in-house, trusted foundry) fabricates the Front End Of Line (FEOL) layers (transistors and lower metal layers) in advanced technology nodes at an untrusted high-end foundry. The Back End Of Line (BEOL) layers (higher metal layers) are then fabricated at the design house's trusted low-end foundry. Split manufacturing is considered secure (prevents reverse engineering and IC piracy) as it hides the BEOL connections from an attacker in the FEOL foundry. We show that an attacker in the FEOL foundry can exploit the heuristics used in typical floorplanning, placement, and routing tools to bypass the security afforded by straightforward split manufacturing. We developed an attack where an attacker in the FEOL foundry can connect 96% of the missing BEOL connections correctly. To overcome this security vulnerability in split manufacturing, we developed a fault analysis-based defense. This defense improves the security of split manufacturing by deceiving the FEOL attacker into making wrong connections.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"42 1","pages":"1259-1264"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77321576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 181

Optical Look Up Table 光学查表

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.184

Zhen Li, S. L. Beux, C. Monat, X. Letartre, I. O’Connor

引用次数: 10

LFSR seed computation and reduction using SMT-based fault-chaining 基于smt的故障链的LFSR种子计算与约简

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.226

Dhrumeel Bakshi, M. Hsiao

引用次数: 3

Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF tests 处理晶圆级模拟/射频测试空间相关性建模中的不连续效应

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.123

K. Huang, Nathan Kupp, J. Carulli, Y. Makris

{"title":"Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF tests","authors":"K. Huang, Nathan Kupp, J. Carulli, Y. Makris","doi":"10.7873/DATE.2013.123","DOIUrl":"https://doi.org/10.7873/DATE.2013.123","url":null,"abstract":"In an effort to reduce the cost of specification testing in analog/RF circuits, spatial correlation modeling of wafer-level measurements has recently attracted increased attention. Existing approaches for capturing and leveraging such correlation, however, rely on the assumption that spatial variation is smooth and continuous. This, in turn, limits the effectiveness of these methods on actual production data, which often exhibits localized spatial discontinuous effects. In this work, we propose a novel approach which enables spatial correlation modeling of wafer-level analog/RF tests to handle such effects and, thereby, to drastically reduce prediction error for measurements exhibiting discontinuous spatial patterns. The core of the proposed approach is a k-means algorithm which partitions a wafer into k clusters, as caused by discontinuous effects. Individual correlation models are then constructed within each cluster, revoking the assumption that spatial patterns should be smooth and continuous across the entire wafer. Effectiveness of the proposed approach is evaluated on industrial probe test data from more than 3,400 wafers, revealing significant error reduction over existing approaches.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"39 1","pages":"553-558"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78073680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Roadmap towards ultimately-efficient zeta-scale datacenters 迈向最终高效的泽塔规模数据中心的路线图

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.1109/HPCSim.2013.6641408

P. Ruch, T. Brunschwiler, S. Paredes, G. Meijer, B. Michel

引用次数: 10

Using synchronization stalls in power-aware accelerators 在功率感知加速器中使用同步会停止

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.091

A. Jooya, A. Baniasadi

引用次数: 1

TreeFTL: Efficient RAM management for high performance of NAND flash-based storage systems TreeFTL:用于高性能NAND闪存存储系统的高效RAM管理

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.086

Chundong Wang, W. Wong

引用次数: 14

Quality-aware media scheduling on MPSoC platforms 基于MPSoC平台的质量感知媒体调度

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.204

Deepak Gangadharan, S. Chakraborty, Roger Zimmermann

{"title":"Quality-aware media scheduling on MPSoC platforms","authors":"Deepak Gangadharan, S. Chakraborty, Roger Zimmermann","doi":"10.7873/DATE.2013.204","DOIUrl":"https://doi.org/10.7873/DATE.2013.204","url":null,"abstract":"Applications that stream multiple video/audio or video+audio clips are being implemented in embedded devices. A Picture-in-Picture (PiP) application is one such application scenario, where two videos are played simultaneously. Although the PiP application is very efficiently handled in televisions and personal computers by providing maximum quality of service to the multiple streams, it is a difficult task in devices with resource constraints. In order to efficiently utilize the resources, it is essential to derive the necessary processor cycles for multiple video streams such that they are displayed with some prespecified quality constraint. Therefore, we propose a network calculus based formal framework to help schedule multiple media streams in the presence of buffer contraints. Further, our framework also presents a schedulability analysis condition to check if the multimedia streams can be scheduled such that a prespecified quality constraint is satisfied with the available service. We present this framework in the context of a PiP application, but it is applicable in general for multiple media streams. The results obtained using the formal framework were further verified using experiments involving system simulation.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"260 1","pages":"976-981"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76299493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

An automatic tool flow for the combined implementation of multi-mode circuits 一种用于组合实现多模电路的自动工具流

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.174

Brahim Al Farisi, Karel Bruneel, João MP Cardoso, D. Stroobandt

引用次数: 11