AVF-driven parity optimization for MBU protection of in-core memory arrays

M. Maniatakos, M. Michael, Y. Makris
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引用次数: 6

Abstract

We propose an AVF-driven parity selection method for protecting modern microprocessor in-core memory arrays against MBUs. As MBUs constitute more than 50% of the upsets in latest technologies, error correcting codes or physical interleaving are typically employed to effectively protect out-of-core memory structures, such as caches. However, such methods are not applicable to high-performance in-core arrays, due to computational complexity, high delay and area overhead. To this end, we revisit parity as an effective mechanism to detect errors and we resort to pipeline flushing and checkpointing for correction. We demonstrate that optimal parity tree construction for MBU detection is a computationally complex problem, which we then formulate as an integer-linear-program (ILP). Experimental results on Alpha 21264 and Intel P6 in-core memory arrays demonstrate that optimal parity tree selection can achieve great vulnerability reduction, even when a small number of bits are added to the parity trees, compared to simple heuristics. Furthermore, the ILP formulation allows us to find better solutions by effectively exploring the solution space in the presence of multiple parity trees; results show that the presence of 2 parity trees offers a vulnerability reduction of more than 50% over a single parity tree.
avf驱动的核心存储器阵列MBU保护奇偶优化
我们提出了一种avf驱动的奇偶校验选择方法,用于保护现代微处理器核心存储器阵列免受MBUs的侵害。作为生产部构成50%以上的冷门最新技术,错误校正码或物理交叉通常用来有效地保护核外内存结构,如缓存。然而,由于计算复杂性、高延迟和面积开销,这种方法不适用于高性能核内阵列。为此,我们重新审视奇偶校验,将其作为检测错误的有效机制,并借助于流水线刷新和检查点进行纠正。我们证明了MBU检测的最优奇偶树构造是一个计算复杂的问题,然后我们将其表述为整数线性规划(ILP)。在Alpha 21264和Intel P6内核内存阵列上的实验结果表明,与简单的启发式方法相比,即使在奇偶校验树中添加少量比特,最优奇偶校验树选择也可以大大减少漏洞。此外,ILP公式允许我们通过有效地探索存在多个奇偶树的解空间来找到更好的解;结果表明,在单个奇偶校验树上,2个奇偶校验树的存在提供了超过50%的脆弱性减少。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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