微纳电子与智能制造最新文献_第2页

FEA Calculations for Ultra Thin Piezoresistive Pressure Sensor on SOI for Heatspreader Integration 用于散热器集成的SOI超薄压阻压力传感器的有限元计算

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1643958

B. Bercu, L. Montès, P. Morfouli

引用次数: 5

Multiphysics Softwares Benchmark on Ansys / Comsol Applied For RF MEMS Switches Packaging Simulations 基于Ansys / Comsol的多物理场软件基准测试应用于RF MEMS开关封装仿真

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1644011

D. Peyrou, P. Pons, H. Granier, D. Leray, A. Ferrand, K. Yacine, M. Saadaoui, A. Nicolas, J. Tao, R. Plana

引用次数: 7

Measuring the Strength of Brittle Microbeams Without Measuring Forces or Displacements 不测量力或位移而测量脆性微梁的强度

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1643990

A. Hirshberg, D. Elata

引用次数: 0

Analytic Model of the Deflection of Piezoelectric Unimorph and Bimorph Structures with Numerical Verification 压电单晶片和双晶片结构挠曲的解析模型及数值验证

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1643989

D. Elata, E. Elka, H. Abramovich

引用次数: 0

Modeling of the Fabrication and Operation of 3-D Self-Assembled SOI MEMS 三维自组装SOI MEMS的制造与运行建模

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1643957

C. Méndez, C. Louis, S. Paquay, P. De Vincenzo, I. Klapka, V. Rochus, F. Iker, N. André, J. Raskin

引用次数: 0

Efficient Damage Sensitivity Analysis of advanced Cu Low-k Bond Pad Structures Using Area Release Energy 基于面积释放能量的新型铜低钾键垫结构损伤灵敏度分析

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1644041

O. van der Sluis, R. Engelen, W. V. van Driel, M. van Gils, R. van Silfhout

{"title":"Efficient Damage Sensitivity Analysis of advanced Cu Low-k Bond Pad Structures Using Area Release Energy","authors":"O. van der Sluis, R. Engelen, W. V. van Driel, M. van Gils, R. van Silfhout","doi":"10.1109/ESIME.2006.1644041","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1644041","url":null,"abstract":"This paper presents an efficient method to describe the damage sensitivity of three-dimensional multi-layered structures. The index that characterizes this failure sensitivity is an energy measure called the area release energy, which predicts the amount of energy that is released upon crack initiation at an arbitrary position along an interface. The benefits of the method are: (1) the criterion can be used as damage sensitivity indicator for complex three-dimensional structures; (2) the criterion is energy based, thus more accurate than stress-based criteria; (3) unlike fracture mechanics, no initial defect size and location has to be assumed a priori. For the development of state-of-the-art CMOS technologies, the integration and introduction of low-k materials are one of the major bottlenecks due to their bad thermal and mechanical integrity and the inherited week interfacial adhesion. The use of ultra low-k (ULK) materials, such as porous dielectrics, will require significant development effort in order to result in reliable interconnect structures that are able to withstand the IC, packaging and assembly related thermo-mechanical and mechanical forces. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily result in cracking, delamination and chipping of the IC back-end structure if no appropriate measures are taken","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"190 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77724957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Interfacial Adhesion Method for Semiconductor Applications Covering the Full Mode Mixity 覆盖全模混合半导体应用的界面粘附方法

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1643963

J. Thijsse, W. V. van Driel, M. van Gils, O. van der Sluis

引用次数: 6

SOI Die Heat Transfer Analysis from Device to Assembly Package SOI模具从器件到装配包的传热分析

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1643947

S. Irving, Y. Liu, D. Connerny, T. Luk

引用次数: 9

Design for Reliability of Wafer Level Packages 晶圆级封装的可靠性设计

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1643961

W. Driel, H. P. Hochstenbach, Guoqi Zhang

{"title":"Design for Reliability of Wafer Level Packages","authors":"W. Driel, H. P. Hochstenbach, Guoqi Zhang","doi":"10.1109/ESIME.2006.1643961","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643961","url":null,"abstract":"Wafer level packages are one of the most advanced packaging concepts. It combines the advantages of flip chip with conventional surface mount technologies. In recent years we have seen a tremendous growth in the application of wafer level packages, both in quantities as well as in the number of products where they are implemented. The technology is, however, not without it's challenges with 1st and 2nd level reliability issues. For instance, the limit on the size of wafer level packages has to do with the 2nd level, or solder bump, reliability. This paper highlights our major research and development results on understanding and enhancing the 1st and 2nd level reliability of wafer level packages using combined experimental and virtual prototyping (thermal, mechanical and thermo-mechanical) techniques. Typical 1st level reliability problems within wafer level packages are cracking of repassivation materials, fatigue of bond over active pads, and cracks within the under bump metallisation. To investigate the physics of failure for these problems, dedicated parametric finite element models are constructed including the thin IC layers. Different repassivation materials and different structures are explored to their potential reliability benefits. By combining the experimental results with reliability prediction models and advanced simulation-based optimisation methods, the complete wafer level package design space in terms of distance from neutral point, PCB thickness, PCB copper layout, and use of improved structures is explored. Our numerical results explain the experimentally obtained reliability results for the effects of package size and PCB thickness. Even more, they indicate that by properly designing the copper layout in the PCB, a 10-20% improvement can be achieved for the WLP 2nd level reliability","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":"118 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76448542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Thermo-Electric Simulation of a 77GHz Radar Transmitter Chip for Automotive Applications 77GHz汽车雷达发射机芯片的热电仿真

微纳电子与智能制造 Pub Date : 2006-04-24 DOI: 10.1109/ESIME.2006.1643998

A. Augustin, T. Hauck, A. Ghazinour

引用次数: 1