Electronic Materials Letters最新文献_第2页

Inorganic Halide Perovskite Quantum Dots for Memristors 忆阻器用无机卤化物钙钛矿量子点

IF 2.1 4区材料科学

Electronic Materials Letters Pub Date : 2025-03-06 DOI: 10.1007/s13391-025-00560-0

Hyo Min Cho, Ho Won Jang

{"title":"Inorganic Halide Perovskite Quantum Dots for Memristors","authors":"Hyo Min Cho, Ho Won Jang","doi":"10.1007/s13391-025-00560-0","DOIUrl":"10.1007/s13391-025-00560-0","url":null,"abstract":"<div><p>Memristor, a combination of memory and resistor, was first proposed as the fourth fundamental passive circuit element. While halide perovskites have emerged as promising materials for memristor devices, organic-inorganic hybrid perovskites face challenges such as hygroscopicity and thermal instability, limiting their long-term applicability. This paper focuses on inorganic halide perovskite quantum dots (IHPQDs), which offer enhanced environmental stability and unique properties, including high tolerance to native defects and ion migration capability. This paper provides a comprehensive review of recent advancements in IHPQDs, covering their crystal structures, synthesis techniques, and operational mechanisms in memristor devices. Unlike previous studies that predominantly explored bulk halide perovskites, we emphasize the role of IHPQDs in resistive switching memory and neuromorphic computing, highlighting their potential for multilevel resistance states and low-power operation. Additionally, this review addresses practical challenges, including thin-film uniformity, charge transport layer integration, and lead-free alternatives, which are critical for the commercialization of IHPQDs-based memristors. By proposing actionable strategies and future research directions, we aim to bridge the gap between fundamental research and real-world applications, positioning IHPQDs as key materials for next-generation electronic devices.</p><h3>Graphical Abstract</h3><div><figure><div><div><picture><source><img></source></picture></div></div></figure></div></div>","PeriodicalId":536,"journal":{"name":"Electronic Materials Letters","volume":"21 3","pages":"291 - 310"},"PeriodicalIF":2.1,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s13391-025-00560-0.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

3D Integrated Process and Hybrid Bonding of High Bandwidth Memory (HBM) 高带宽存储器（HBM）的三维集成工艺与混合键合

IF 2.1 4区材料科学

Electronic Materials Letters Pub Date : 2025-03-02 DOI: 10.1007/s13391-025-00557-9

Chae Yeon Lee, Chae Ho Won, Seyeon Jung, Eun Su Jung, Tae Min Choi, Hwa Rim Lee, JinUk Yoo, Songhun Yoon, Sung Gyu Pyo

{"title":"3D Integrated Process and Hybrid Bonding of High Bandwidth Memory (HBM)","authors":"Chae Yeon Lee, Chae Ho Won, Seyeon Jung, Eun Su Jung, Tae Min Choi, Hwa Rim Lee, JinUk Yoo, Songhun Yoon, Sung Gyu Pyo","doi":"10.1007/s13391-025-00557-9","DOIUrl":"10.1007/s13391-025-00557-9","url":null,"abstract":"<div><p>This review paper systematically analyzes the recent advancements in semiconductor packaging technology, focusing on hybrid bonding technology. Hybrid bonding is a crucial technique for enhancing integration density and thermal management in high-performance semiconductor devices by directly bonding metal to an insulator. It is categorized into wafer-to-wafer (W2W), die-to-wafer (D2W), and die-to-die (D2D) methods.</p><p>This paper compares the characteristics, advantages, and limitations of each method while presenting technical approaches for performance improvements. Innovations such as new dielectric materials, surface and interface modifications, and optimizing the crystallinity and crystal orientation of metals can significantly enhance the reliability and performance of hybrid bonding. These strategies boost data transfer rates between memory and processors while reducing power consumption and improving overall system performance. This latest research on maximizing hybrid bonding performance is also discussed, emphasizing its potential in the next generation of memory technologies, including high bandwidth memory. This research lays a critical foundation for further advancements in high-performance 3D integrated circuit technology.</p><h3>Graphical Abstract</h3>\u0000<div><figure><div><div><picture><source><img></source></picture></div></div></figure></div></div>","PeriodicalId":536,"journal":{"name":"Electronic Materials Letters","volume":"21 3","pages":"395 - 419"},"PeriodicalIF":2.1,"publicationDate":"2025-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhancement Mode in ZnSnO Thin-Film Transistors with Ultrathin Al2O3 Contact Layer 超薄Al2O3接触层ZnSnO薄膜晶体管的增强模式

IF 2.1 4区材料科学

Electronic Materials Letters Pub Date : 2025-02-25 DOI: 10.1007/s13391-025-00554-y

Zihan Wang, Jiaqi Zhang, Ruqi Yang, Dunan Hu, Zhizhen Ye, Jianguo Lu

{"title":"Enhancement Mode in ZnSnO Thin-Film Transistors with Ultrathin Al2O3 Contact Layer","authors":"Zihan Wang, Jiaqi Zhang, Ruqi Yang, Dunan Hu, Zhizhen Ye, Jianguo Lu","doi":"10.1007/s13391-025-00554-y","DOIUrl":"10.1007/s13391-025-00554-y","url":null,"abstract":"<div><p>ZnSnO-based thin-film transistor (TFT) is considered to be the most competitive candidate for next-generation displays and transparent electronics. However, ZnSnO TFTs usually work in depletion mode with a negative voltage. In this work, we designed a structure of ZnSnO/Al<sub>2</sub>O<sub>3</sub> TFTs with ultrathin Al<sub>2</sub>O<sub>3</sub> contact layers. As the thickness of tunnel layer increases, the threshold voltages of TFTs increase at first and then decrease. When the growth cycle of Al<sub>2</sub>O<sub>3</sub> layer reaches 17 (with thickness of ∼ 2 nm), the TFT has a positive threshold voltage of 2.3 V, as well as the best performances with an on-to-off current ratio of ∼ 10<sup>6</sup>, a saturation mobility of 23.5 cm<sup>2</sup>V<sup>− 1</sup>s<sup>− 1</sup>, and a small subthreshold swing of 0.57 V/decade. In this study, for the first time we propose an ultrathin contact method to modify the threshold voltage of amorphous oxide semiconductor (AOS) TFTs to get the enhancement mode without sacrificing mobility. It is expected that the method may open the door for practical applications of ZnSnO-based AOS TFTs.</p><h3>Graphical Abstract</h3><div><figure><div><div><picture><source><img></source></picture></div></div></figure></div></div>","PeriodicalId":536,"journal":{"name":"Electronic Materials Letters","volume":"21 3","pages":"337 - 345"},"PeriodicalIF":2.1,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hydroxyethyl Cellulose Charge Trap Layer for Water-Degradable Short-Term Transistor Memory 用于水可降解短期晶体管存储器的羟乙基纤维素电荷阱层

IF 2.1 4区材料科学

Electronic Materials Letters Pub Date : 2025-02-22 DOI: 10.1007/s13391-025-00553-z

Jeong-In Lee, Baeksang Sung, Joo Won Han, Yong Hyun Kim, Jonghee Lee, Min-Hoi Kim

{"title":"Hydroxyethyl Cellulose Charge Trap Layer for Water-Degradable Short-Term Transistor Memory","authors":"Jeong-In Lee, Baeksang Sung, Joo Won Han, Yong Hyun Kim, Jonghee Lee, Min-Hoi Kim","doi":"10.1007/s13391-025-00553-z","DOIUrl":"10.1007/s13391-025-00553-z","url":null,"abstract":"<div><p>This study demonstrates the performance of a hydroxyethyl cellulose (HEC) charge trap layer for p-type organic thin-film transistor memory. The HEC charge trap transistor memory (HEC-TM) shows conventional charge trapping characteristics; that is, positive and negative threshold voltage (<i>V</i><sub>th</sub>) shifts after the application of a positive and negative bias, respectively. As the time and amplitude of the gate bias increases, <i>V</i><sub>th</sub> shift increases gradually and saturates. Because the electron trap is relatively more dominant than the hole trap in the hydroxyl group of HEC, a larger shift in <i>V</i><sub>th</sub> and longer memory retention appears when a positive voltage is applied rather than a negative voltage. HEC-TM is immersed and the HEC charge trap layer (HEC-CTL) is dissolved sufficiently with deionized water to validate its water degradability. HEC-TM is expected to be utilized as a biodegradable short-term transistor memory device.</p><h3>Graphic Abstract</h3>\u0000<div><figure><div><div><picture><source><img></source></picture></div></div></figure></div></div>","PeriodicalId":536,"journal":{"name":"Electronic Materials Letters","volume":"21 3","pages":"357 - 365"},"PeriodicalIF":2.1,"publicationDate":"2025-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Correction: Thickness-Dependent Electrical and Optoelectrical Properties of SnSe2 Field-Effect Transistors 修正：SnSe2场效应晶体管的厚度相关电学和光电学特性

IF 2.1 4区材料科学

Electronic Materials Letters Pub Date : 2025-02-21 DOI: 10.1007/s13391-025-00552-0

Han-Woong Choi, Dong Hyun Seo, Ji Won Heo, Sang-Il Kim, TaeWan Kim

引用次数: 0

Enhancing High-Frequency Magnetic Performance of Fe-Based Amorphous Alloy Powders Coated with Insulating Glass Frits 中空玻璃熔块包覆铁基非晶合金粉末高频磁性能的研究

IF 2.1 4区材料科学

Electronic Materials Letters Pub Date : 2025-02-15 DOI: 10.1007/s13391-025-00550-2

Seung-Wook Kim, Tae-Kyung Lee, Ye-Ji Son, Hyo-Min Kim, Dae-Yong Jeong

{"title":"Enhancing High-Frequency Magnetic Performance of Fe-Based Amorphous Alloy Powders Coated with Insulating Glass Frits","authors":"Seung-Wook Kim, Tae-Kyung Lee, Ye-Ji Son, Hyo-Min Kim, Dae-Yong Jeong","doi":"10.1007/s13391-025-00550-2","DOIUrl":"10.1007/s13391-025-00550-2","url":null,"abstract":"<div><p>Amorphous metal powders, known for their high saturation magnetization, low coercivity (<i>H</i><sub><i>c</i></sub>), and reduced eddy current loss, hold great promise for high-performance magnetic devices. However, elevated core losses at higher frequencies—primarily due to eddy currents—impair their efficiency, leading to significant heat dissipation. This study addresses this challenge by investigating the application of low-softening temperature (<i>T</i><sub><i>s</i></sub>) glass frits as an insulating coating to enhance the electrical and magnetic properties of Fe<sub>92.3</sub>Si<sub>3.5</sub>B<sub>3.0</sub>C<sub>0.7</sub>P<sub>0.5</sub> (<i>wt</i>%) amorphous alloy powders. The practical implications of this research are significant, as it offers a potential solution to the problem of core losses at higher frequencies. The coated powders exhibited superior performance, with the lowest core loss measured at less than 321 mW/cm³ (<i>B</i><sub><i>m</i></sub> = 0.2 T at 1 MHz) and a high powder resistivity of up to 1.81 × 10<sup>9</sup> Ω∙cm while maintaining appropriate permeability. Calculation and experimental results demonstrated that adjusting the coating thickness and ensuring a uniform layer minimized inter-particle and intra-particle eddy current losses. This optimization led to a significant reduction in core loss, enhancing the material’s high-frequency performance. The study emphasizes the critical role of low <i>T</i><sub><i>s</i></sub> glass frits in balancing resistivity, magnetic properties, and core loss reduction, offering a practical pathway for developing efficient amorphous alloy powders for advanced magnetic applications, including compact inductors and energy-efficient devices in eco-friendly technologies.</p><h3>Graphical Abstract</h3><div><figure><div><div><picture><img></picture></div></div></figure></div></div>","PeriodicalId":536,"journal":{"name":"Electronic Materials Letters","volume":"21 2","pages":"200 - 206"},"PeriodicalIF":2.1,"publicationDate":"2025-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143571108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Soft Magnetic Properties of Amorphous ring Cores Prepared via Spark Plasma Sintering Using Fe-based Amorphous Powders (Fe, Co)68.7(C, Si, B, P)24.5(Mo, Al)6.8 Fe基非晶粉末（Fe, Co）68.7(C, Si， B， P)24.5（Mo, Al）烧结制备非晶环芯的软磁性能

IF 2.1 4区材料科学

Electronic Materials Letters Pub Date : 2025-02-13 DOI: 10.1007/s13391-025-00549-9

Jae-Won Lee, Jin-Ah Kim, In-Joon Sohn, Kyyoul Yun, Seonghoon Yi

{"title":"Soft Magnetic Properties of Amorphous ring Cores Prepared via Spark Plasma Sintering Using Fe-based Amorphous Powders (Fe, Co)68.7(C, Si, B, P)24.5(Mo, Al)6.8","authors":"Jae-Won Lee, Jin-Ah Kim, In-Joon Sohn, Kyyoul Yun, Seonghoon Yi","doi":"10.1007/s13391-025-00549-9","DOIUrl":"10.1007/s13391-025-00549-9","url":null,"abstract":"<div><p>An Fe-based amorphous alloy (Fe, Co)<sub>68.7</sub>(C, Si, B, P)<sub>24.5</sub>(Mo, Al)<sub>6.8</sub> was prepared as amorphous ribbons (~ 25 μm thick) and amorphous rods (Ф3 mm), which were crushed and sieved to form powders with different shapes and particles smaller than 53 μm: amorphous flake powders made from crushed ribbons and amorphous irregular powders made from crushed rods. Both powders were consolidated via spark plasma sintering into dense ring cores with a relative density exceeding 90%; this high density is attributed to the Newtonian flow within the temperature range of the amorphous powder’s supercooled liquid region. Excellent soft magnetic properties originating from the amorphous nature and high density of the ring cores were confirmed. Additionally, due to electrical isolation between the powder particles, the eddy current loss of the amorphous ring cores made from the SiO<sub>2</sub>-coated amorphous flake powder was significantly reduced to 4.86 W/kg (at Bm = 100 mT, 1 kHz).</p><h3>Graphical Abstract</h3><div><figure><div><div><picture><source><img></source></picture></div></div></figure></div></div>","PeriodicalId":536,"journal":{"name":"Electronic Materials Letters","volume":"21 3","pages":"346 - 356"},"PeriodicalIF":2.1,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Kinetic Investigation of CuSx Formation on Cu Substrates for Enhanced Electrochemical CO2 Reduction to HCOOH Cu衬底上CuSx形成的电化学强化CO2还原成HCOOH的动力学研究

IF 2.1 4区材料科学

Electronic Materials Letters Pub Date : 2025-02-13 DOI: 10.1007/s13391-025-00546-y

Jin Wook Lim, Won Seok Cho, Jong-Lam Lee

{"title":"Kinetic Investigation of CuSx Formation on Cu Substrates for Enhanced Electrochemical CO2 Reduction to HCOOH","authors":"Jin Wook Lim, Won Seok Cho, Jong-Lam Lee","doi":"10.1007/s13391-025-00546-y","DOIUrl":"10.1007/s13391-025-00546-y","url":null,"abstract":"<div><p>Copper sulfide (CuS<sub>x</sub>) is an electrocatalyst which selectively converts CO<sub>2</sub> into HCOOH under harsh conditions. Here, we investigate the formation and kinetics of CuS<sub>x</sub> nanostructures on various multi-metal substrates to understand their catalytic properties in sulfur-containing environments. Using a combination of morphological, structural, and electrochemical analyses, we elucidate the time-dependent growth behavior of CuS<sub>x</sub> nanostructures with progressive void formation over time. Notably, we discover that CuS<sub>x</sub> formation is accelerated on substrates with galvanic corrosion-promoting metals such as Ag and Au, leading to enhanced selectivity for HCOOH during CO<sub>2</sub> reduction. In contrast, coating Cu with corrosion-inhibiting metals like Sn, Ni, or In reduce HCOOH selectivity, highlighting the critical role of galvanic corrosion in the CuS<sub>x</sub> formation mechanism and its kinetics. This study experimentally identifies the impact of galvanic corrosion on CuS<sub>x</sub> formation mechanisms and offers insights for optimizing electrocatalytic systems.</p><h3>Graphical Abstract</h3><div><figure><div><div><picture><source><img></source></picture></div></div></figure></div></div>","PeriodicalId":536,"journal":{"name":"Electronic Materials Letters","volume":"21 2","pages":"245 - 251"},"PeriodicalIF":2.1,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143570987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Adaptable Low-Temperature Resistor Standard Composed of ITO thin Film 可适应低温电阻标准由ITO薄膜组成

IF 2.1 4区材料科学

Electronic Materials Letters Pub Date : 2025-02-11 DOI: 10.1007/s13391-025-00548-w

Sebastian Złotnik, Małgorzata Nyga, Przemysław Morawiak, Witold Rzodkiewicz, Patryk Bruszewski, Marek A. Kojdecki, Jerzy Wróbel, Jarosław Wróbel

{"title":"Adaptable Low-Temperature Resistor Standard Composed of ITO thin Film","authors":"Sebastian Złotnik, Małgorzata Nyga, Przemysław Morawiak, Witold Rzodkiewicz, Patryk Bruszewski, Marek A. Kojdecki, Jerzy Wróbel, Jarosław Wróbel","doi":"10.1007/s13391-025-00548-w","DOIUrl":"10.1007/s13391-025-00548-w","url":null,"abstract":"<div><p>Herein, we present indium tin oxide (ITO) as a promising candidate for developing adaptable standard resistors. The ITO thin-film device structures exhibit an average resistivity of approx. 1.5 × 10<sup>–4</sup> Ω ⋅ cm, demonstrating remarkable stability in resistance values over time and showcasing temperature-independent magnetoresistance, making them reliable for various applications. ITO resistor structures were found to be optimal with an area ≥10<sup>–7</sup> cm<sup>2</sup>, without observed additional series resistance. The temperature dependence of resistance values changes by approx. 10% within a broad temperature range of 5–310 K in a predictable and repeatable way. Unlike traditional 2D materials, ITO can be processed without the necessity of a protective layer, facilitating easier integration into electronic circuits. Moreover, ITO demonstrates single-type electron characteristics, without hole-like contributions, being particularly suitable as a charge carrier transport control. Our experimental findings indicate that resistors made of ITO-coated glass thin films present a viable alternative to standard chip-type passive components, which are commonly used in electronic devices. This work highlights the potential of ITO as a durable and flexible material for advanced electronics, enabling the design of next-generation resistive elements that can adapt to varying operational conditions.</p><h3>Graphical Abstract</h3><div><figure><div><div><picture><source><img></source></picture></div></div></figure></div></div>","PeriodicalId":536,"journal":{"name":"Electronic Materials Letters","volume":"21 2","pages":"193 - 199"},"PeriodicalIF":2.1,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s13391-025-00548-w.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143571060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Dielectric Bonding Method for 3D Integration Packaging Using Self-Assembled Monolayer 自组装单层三维集成封装的介电键合方法

IF 2.1 4区材料科学

Electronic Materials Letters Pub Date : 2025-02-08 DOI: 10.1007/s13391-025-00547-x

Wonbin Kim, Sungjae Choi, Seongi Lee, Young-Chang Joo, Byoung-Joon Kim

{"title":"Dielectric Bonding Method for 3D Integration Packaging Using Self-Assembled Monolayer","authors":"Wonbin Kim, Sungjae Choi, Seongi Lee, Young-Chang Joo, Byoung-Joon Kim","doi":"10.1007/s13391-025-00547-x","DOIUrl":"10.1007/s13391-025-00547-x","url":null,"abstract":"<div><p>The emergence of big data and artificial intelligence has promoted the semiconductor industry to increasingly adopt advanced three-dimensional stacking packaging technologies due to the limitations of device scaling. Traditional packaging methods, which rely on micro bumps and adhesives, struggle to meet the growing demands for sub-micrometer fine pitches. To address these challenges, bump-less direct bonding techniques, such as Cu/SiO₂ hybrid bonding, have gained attention, along with surface-activated bonding (SAB) using plasma treatment. However, plasma treatment poses risks, including Cu oxidation and potential short circuits from Cu particle transfer in fine-pitch applications. This study presents a novel plasma-free method that utilizes self-assembled monolayers (SAMs), thin molecular layers that spontaneously create ordered structures on surfaces, for dielectric surface activation. We deposited 3-aminopropyltriethoxysilane (APTES) on silicon dioxide (SiO₂), resulting in a hydrophilic layer that enhances bonding. Notably, a heat treatment significantly improved interfacial adhesion strength through the formation of an amorphous silicon (Si) layer. This SAM-based bonding technique, which enables dielectric surface without the need for plasma, holds promise for future fine-pitch hybrid bonding applications in 3D integrated packaging.</p><h3>Graphical abstract</h3><div><figure><div><div><picture><source><img></source></picture></div></div></figure></div></div>","PeriodicalId":536,"journal":{"name":"Electronic Materials Letters","volume":"21 2","pages":"184 - 192"},"PeriodicalIF":2.1,"publicationDate":"2025-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143571147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0