Microprocessors and Microsystems最新文献

{"title":"Advantages of unsupervised learning analysis methods in single-trace SCA attacks","authors":"Marcin Aftowicz ,&nbsp;Ievgen Kabin ,&nbsp;Zoya Dyka ,&nbsp;Peter Langendoerfer","doi":"10.1016/j.micpro.2023.104994","DOIUrl":"10.1016/j.micpro.2023.104994","url":null,"abstract":"<div><p><span><span><span><span>Machine learning techniques<span> are commonly employed in the context of Side Channel Analysis attacks. The </span></span>clustering algorithms can be successfully used as classifiers in single execution attacks against implementations of </span>Elliptic Curve </span>point multiplication known as </span><em>kP</em> operation. They can distinguish between the processing of ‘ones’ and ‘zeros’ during secret scalar processing in the binary <em>kP</em><span> algorithm. The successful SCA performed by designers can aid in recognizing the leakage sources in cryptographic designs and lead to improvement of the cryptographic implementations. In this work we investigate the influence of the hamming weight of scalar </span><em>k</em><span> on the success rate of the single-trace attack. We used the clustering method </span><em>K-means</em> and the statistical method <em>the comparison to the mean</em><span>. We analysed simulated power traces and power traces of an FPGA implementation to conclude that </span><em>K-means</em>, unlike <em>the comparison to the mean</em>, was able to deal with extracting the scalar even when it is consisted of less than 30% of ‘ones’ and more than 70% of ‘ones’.</p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"105 ","pages":"Article 104994"},"PeriodicalIF":2.6,"publicationDate":"2023-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139062412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Implementation of survivability aware protocols in WSN for IoT applications using Contiki-OS and hardware testbed evaluation","authors":"Manu Elappila ,&nbsp;Suchismita Chinara","doi":"10.1016/j.micpro.2023.104988","DOIUrl":"10.1016/j.micpro.2023.104988","url":null,"abstract":"<div><p>The Internet of Things<span><span> is a network of devices capable of operating and communicating individually and working for a specific goal collectively. Technologically, many networking and computing mechanisms have to work together with a common objective for the IoT<span><span> applications to function, and many sensing and actuating devices have to get connected to the Internet backbone. The networks of resource-constrained sensor devices constitute an integral part of IoT application networks. Network survivability is a critical aspect to consider in the case of a network of low-power, resource-constrained devices. Algorithms at different layers of the protocol stack have to work collectively to enhance the survivability of the application network. In this article, the survivability-aware protocols for </span>wireless sensor networks for IoT applications are implemented in real network scenarios. The routing strategy, Survivable Path Routing protocol, and the channel allocation technique, Survivability Aware Channel Allocation, are implemented in Contiki-OS, the open-source operating system for IoT. Furthermore, the implementation scenarios are tested with the FIT IoT Lab hardware </span></span>testbed. Simulated results are compared with the results obtained from the testbed evaluation.</span></p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 104988"},"PeriodicalIF":2.6,"publicationDate":"2023-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139062360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A real-time SVM-based hardware accelerator for hyperspectral images classification in FPGA","authors":"Lucas Amilton Martins ,&nbsp;Felipe Viel ,&nbsp;Laio Oriel Seman ,&nbsp;Eduardo Augusto Bezerra ,&nbsp;Cesar Albenes Zeferino","doi":"10.1016/j.micpro.2023.104998","DOIUrl":"10.1016/j.micpro.2023.104998","url":null,"abstract":"<div><p><span>Hyperspectral imaging<span><span> can be conceptualized as a three-dimensional dataset of spectral information related to a particular landscape. Generally speaking, these are aerial photographs captured by Earth observation satellites. A useful analogy for a </span>hyperspectral image<span> is one of a cube formed with the image acquired along the X and Y axes and a third dimension of spectral bands of varying wavelengths. Given the wealth of data contained within these images, they have been employed in both civilian and military applications such as terrain recognition, urban development supervision, recognition of rare minerals, and various other objectives. The increased utilization of these images has garnered the interest of researchers striving to create solutions that may enable faster processing of the images via </span></span></span>parallel processing<span>. In this context, FPGA<span><span> technology is an option capable of facilitating the implementation of such a system for observation satellites. This research is situated within this framework and aims to develop an FPGA-synthesized hardware accelerator to facilitate real-time hyperspectral image categorization. By taking this approach, hardware-specific solutions can be implemented for embedded applications that process hyperspectral images and can also be integrated with further </span>image processing<span> steps. The proposed accelerator was constructed based on an advanced algorithmic model, resulting in outcomes consistent with those generated by the software-based solution. The experimental results demonstrate that the engineered accelerator can attain a pixel classification time equal to or less than the pixel acquisition time, thus conforming to the real-time processing criteria concerning classification time. Further, the manufactured accelerator exhibits scalability that can classify distinct datasets with varying classes concurrently while maintaining a uniform logic resource utilization.</span></span></span></p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 104998"},"PeriodicalIF":2.6,"publicationDate":"2023-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139062414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Abeto: An automated benchmarking tool to manage heterogeneous IP core databases","authors":"Antonio J. Sánchez ,&nbsp;Yubal Barrios ,&nbsp;Lucana Santos ,&nbsp;Roberto Sarmiento","doi":"10.1016/j.micpro.2023.104987","DOIUrl":"10.1016/j.micpro.2023.104987","url":null,"abstract":"<div><p>System-level design makes use of building blocks, known as soft IP cores, to build complex developments. The usage of these IP cores allows to reduce design and verification time, and also to save costs. However, the use of third-party IP cores tends to present difficulties because of a lack of standardization in their organization, distribution and management, which derive in heterogeneous databases. Most of the time, system developers need to describe some additional code to enable the integration, verification and validation of the IP core, which is not available as part of their distribution. This implies acquiring a deep knowledge of each IP core, often with a large learning curve.</p><p>In this work Abeto is presented, a new software tool for IP core databases management. It allows to easily integrate and use a heterogeneous group of IP cores, described in VHDL, with a unified set of instructions or commands. In order to do so, Abeto requires from every IP core some side information about its packaging and how to operate with the IP. Currently, Abeto provides support for a set of well-known EDA tools and has been successfully applied to the European Space Agency portfolio of IP cores for benchmarking purposes. To demonstrate its performance, mapping results for these IP cores on the novel NanoXplore BRAVE FPGA family are provided.</p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 104987"},"PeriodicalIF":2.6,"publicationDate":"2023-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0141933123002326/pdfft?md5=e94fcf9e16ab0ae8c28dbba99e96660d&pid=1-s2.0-S0141933123002326-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139094372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Deep neural networks accelerators with focus on tensor processors","authors":"Hamidreza Bolhasani ,&nbsp;Mohammad Marandinejad","doi":"10.1016/j.micpro.2023.105005","DOIUrl":"10.1016/j.micpro.2023.105005","url":null,"abstract":"<div><p><span>The massive amount of data and the problem of processing them is one of the main challenges of the digital age, and the development of artificial intelligence and </span>machine learning<span> can be useful in solving this problem. Using deep neural networks<span> to improve the efficiency of these two areas is a good solution. So far, several architectures have been introduced for data processing with the benefit of deep neural networks, whose accuracy, efficiency, and computing power are different from each other. This article tries to review these architectures, their features, and their functions in a systematic way. According to the current research style, 24 articles (conference and research articles related to this topic) have been evaluated in the period of 2014–2022. In fact, the significant aspects of the selected articles are compared and at the end, the upcoming challenges and topics for future research are presented. The results show that the main parameters for proposing a new tensor processor include increasing speed and accuracy and reducing data processing time, reducing on-chip storage space, reducing DRAM access, reducing energy consumption, and achieving high efficiency.</span></span></p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"105 ","pages":"Article 105005"},"PeriodicalIF":2.6,"publicationDate":"2023-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139062366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel low hardware configurable ring oscillator (CRO) PUF for lightweight security applications","authors":"Husam Kareem,&nbsp;Dmitriy Dunaev","doi":"10.1016/j.micpro.2023.104989","DOIUrl":"10.1016/j.micpro.2023.104989","url":null,"abstract":"<div><p>Physical unclonable function (PUF) is a promising hardware security primitive that can generate a unique secret key peculiar to each chip by extracting the differences of non-reproducible manufacturing variations for the same implementations. Although there are several types of PUF designs and structures, ring oscillator (RO) PUF is one of the most prominent PUFs due to its straightforward implementation and remarkable performance. However, the traditional RO-PUF does not support large sizes of input/output combinations or challenge-response pairs (CRPs), as it is called in the scope of PUFs. Consequently, RO-PUF is more vulnerable to adversary attacks which can reveal the PUFs’ CRPs using a machine learning approach. Increasing the size of RO-PUF's CRPs requires a high increase in the circuit size leading to unacceptable area overhead for lightweight applications. The primary technique used to increase RO-PUF CRPs’ size without increasing the size of the required hardware is to develop a configurable ring oscillator (CRO) PUF. In this paper, we propose a configurable logic unit (CLU) that can be utilized to build a low-hardware CRO-PUF. The proposed CLU consists of a 1-XOR gate and a 1-XNOR gate. Building a CRO-PUF using the proposed CLU dramatically increases the CRPs size while minimizing the required hardware. The proposed CRO-PUF achieves excellent evaluation results, with measured uniqueness of 50.1 %, uniformity of 49.45 %, and reliability of 98.33 %. These values are in close proximity to the ideal targets of 50 % for uniqueness and uniformity, and 100 % for reliability</p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 104989"},"PeriodicalIF":2.6,"publicationDate":"2023-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S014193312300234X/pdfft?md5=701fd3d90bd65a2ed764a13232d9a6bb&pid=1-s2.0-S014193312300234X-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139036640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Experimental evaluation of RISC-V micro-architecture against fault injection attack","authors":"Maryam Esmaeilian,&nbsp;Hakem Beitollahi","doi":"10.1016/j.micpro.2023.104991","DOIUrl":"10.1016/j.micpro.2023.104991","url":null,"abstract":"<div><p><span>Today, the use of embedded processors is increasing dramatically and they are used in all aspects from our daily life to security applications. Physical access to hardware has made the hardware security a major concern. Hardware attacks compromise the hardware security by physically accessing target devices. Among the available techniques for hardware attacks, Fault Injection<span> Attacks (FIAs), such as clock glitching, are one of the most harmful types of non-invasive attacks that can disrupt the operation of an embedded system. Thus, it will be important and fundamental to evaluate </span></span>embedded software<span> programs before using them in critical applications and check their vulnerability against fault injection attacks. However, it is often difficult for software developers to assess vulnerabilities. In this paper, an easy-to-use platform is presented to facilitate the process of evaluating the vulnerability of programs running on embedded processors against clock glitching attacks. Our experimental results show the vulnerability window of RISC-V micro-architecture for different high-level C-functions. The results of this research can help the developers of embedded systems that are used in security applications to evaluate their system against clock glitching attacks with the least cost in a short time.</span></p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 104991"},"PeriodicalIF":2.6,"publicationDate":"2023-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139026463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improved DWT and IDWT architectures for image compression","authors":"Ritesh Sur Chowdhury,&nbsp;Jhilam Jana,&nbsp;Sayan Tripathi,&nbsp;Jaydeb Bhaumik","doi":"10.1016/j.micpro.2023.104990","DOIUrl":"10.1016/j.micpro.2023.104990","url":null,"abstract":"<div><p><span><span>In the recent era, a rapid development in the field of image processing<span> has been observed. One of the important applications in image processing is compression. Several wavelet transform based </span></span>image compression<span><span> techniques have already been introduced. In this paper, Discrete Wavelet Transform (DWT) and Inverse Discrete Wavelet Transform (IDWT) based improved image compression and decompression techniques have been proposed by incorporating a scaling factor. The DWT and IDWT algorithms are implemented using folded architecture. To reduce the usages of hardware resources, a multiplier is recursively used. Image compression and decompression schemes based on proposed DWT and IDWT architectures are tested using four different image databases. The proposed technique provides better results in terms of bits per pixel, compression ratio, </span>mean square error, peak-signal-to-noise ratio, normalized correlation coefficient and structural similarity index. </span></span>FPGA<span> based synthesis has been performed using Xilinx Vivado Synthesis tool in terms of slice LUTs, slice registers, clock frequency, delay and power. The synthesis results show that proposed DWT and IDWT architectures are amenable for image compression and decompression applications.</span></p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 104990"},"PeriodicalIF":2.6,"publicationDate":"2023-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138820588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel partition strategy for efficient implementation of 3D Cellular Genetic Algorithms","authors":"Martín Letras ,&nbsp;Alicia Morales-Reyes ,&nbsp;René Cumplido ,&nbsp;María-Guadalupe Martínez-Peñaloza ,&nbsp;Claudia Feregrino-Uribe","doi":"10.1016/j.micpro.2023.104986","DOIUrl":"10.1016/j.micpro.2023.104986","url":null,"abstract":"<div><p><span><span><span>Solving optimization problems while fulfilling real-time constraints requires high algorithmic and processing performance. Cellular </span>Genetic Algorithms (cGAs) have been competitive at difficult single objective combinatorial and continuous domain problems. Moreover, it has been demonstrated that structural properties in cGAs, such as population topology dimension, local neighborhood configuration and ad-hoc selection mechanisms, allow not only further algorithmic improvement but also, these characteristics can be combined at hardware level for acceleration. In this article, a novel partition strategy to exploit 3D cGAs population dynamics on a 2D processing array using </span>Field Programmable Gate Arrays<span> (FPGAs) as the target processing platform is presented. The proposed architecture fits as an optimization module within an embedded system where real-time constraints must be fulfilled. Therefore, it is important to find an optimal trade-off between hardware resources usage and searching time. Overall results demonstrate that the proposed architecture can run up to 90 MHz when tackling continuous </span></span>benchmark functions<span>. Moreover, speed-up of up to three and two orders of magnitude are achieved in comparison to a single CPU and a parallel GPU respectively.</span></p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 104986"},"PeriodicalIF":2.6,"publicationDate":"2023-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138610571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Retraction notice to “FPGA implementation of PMSG based AC conversion using soft switching twin–mode PWM/FPGA control for high power IM application” [Microprocessors and Microsystems 75 (2020) 103044]","authors":"C. Kadhiravan,&nbsp;J. Baskaran","doi":"10.1016/j.micpro.2023.104977","DOIUrl":"10.1016/j.micpro.2023.104977","url":null,"abstract":"","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 104977"},"PeriodicalIF":2.6,"publicationDate":"2023-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0141933123002223/pdfft?md5=17a61357c1aeda88aa50056adda92d00&pid=1-s2.0-S0141933123002223-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138515481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}