Microprocessors and Microsystems最新文献

{"title":"Edge-sorter: A hardware sorting engine for area & power constrained edge computing devices","authors":"Hakem Beitollahi ,&nbsp;Marziye Pandi ,&nbsp;Mostafa Moghaddas","doi":"10.1016/j.micpro.2024.105006","DOIUrl":"10.1016/j.micpro.2024.105006","url":null,"abstract":"<div><p><span><span>In recent years, hardware sorters have been an attracted topic for researchers. Since hardware sorters play a crucial role in embedded systems, several attempts have been made to efficiently design and implement these sorters. Previous state-of-the-art hardware sorters are not suitable for embedded </span>edge computing devices because they (1) consume high power, (2) occupy high area, (3) work for limited data-width numbers, (4) require many memory resources, and (5) finally, their architecture is not scalable with the number of input records. This paper proposes a hardware sorter for edge devices with limited hardware resources. The proposed hardware sorter, called Edge-Sorter, processes 4 bits of input records at each clock cycle. Edge-Sorter utilizes the unary processing in its main processing core. Edge-Sorter has valuable attributes compared to previous state-of-the-art techniques, including low </span>power consumption, low area occupation, sorting numbers without storing their indices, sorting numbers with arbitrary data-width, and scalable with the number of input records. The proposed approach is evaluated and compared with previous state-of-the-art techniques with two different implementation and synthesis environments: Xilinx Vivado FPGA-based and Synopsys Design Compiler 45-nm ASIC-based. The Synthesis results of both environments indicate that both Edge-Sorter techniques reduces area and power consumption on average by 80% and 90%, respectively compared to previous techniques.</p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"105 ","pages":"Article 105006"},"PeriodicalIF":2.6,"publicationDate":"2024-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139375497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Retraction notice to “real-time monitoring of the athlete's musculoskeletal health based on an embedded processor” [Microprocessors and Microsystems 81 (2021) 103742]","authors":"Rongjun Zhu","doi":"10.1016/j.micpro.2023.104997","DOIUrl":"https://doi.org/10.1016/j.micpro.2023.104997","url":null,"abstract":"","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 104997"},"PeriodicalIF":2.6,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0141933123002429/pdfft?md5=d79373509da79022af1fe62da6dbeb95&pid=1-s2.0-S0141933123002429-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139099686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Retraction notice to “Business English visualization system based on video surveillance and the internet of things” [Microprocessors and Microsystems 80 (2021) 103639]","authors":"Xiaolei Qin","doi":"10.1016/j.micpro.2023.104996","DOIUrl":"10.1016/j.micpro.2023.104996","url":null,"abstract":"","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 104996"},"PeriodicalIF":2.6,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0141933123002417/pdfft?md5=c8e843d7bd40877daf09a4b8b2316af5&pid=1-s2.0-S0141933123002417-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139094342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Micro-architecture that supports the Fano–Elias encoding and a hardware accelerator for approximate membership queries","authors":"Guy Even,&nbsp;Gabriel Marques Domingues","doi":"10.1016/j.micpro.2023.104992","DOIUrl":"10.1016/j.micpro.2023.104992","url":null,"abstract":"&lt;div&gt;&lt;p&gt;&lt;span&gt;We present the first hardware design that supports operations over the Fano–Elias encoding (FE-encoding). Our design is a combinational circuit (i.e., single clock cycle) that supports insertions, deletions, and queries. FE-encoding allows one to store &lt;/span&gt;&lt;span&gt;&lt;math&gt;&lt;mi&gt;f&lt;/mi&gt;&lt;/math&gt;&lt;/span&gt; binary strings, each of length &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;ℓ&lt;/mi&gt;&lt;mo&gt;+&lt;/mo&gt;&lt;mo&gt;log&lt;/mo&gt;&lt;mi&gt;m&lt;/mi&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt; using a string that is &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;m&lt;/mi&gt;&lt;mo&gt;+&lt;/mo&gt;&lt;mi&gt;f&lt;/mi&gt;&lt;mo&gt;+&lt;/mo&gt;&lt;mi&gt;f&lt;/mi&gt;&lt;mi&gt;ℓ&lt;/mi&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt; bits long (rather than &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;f&lt;/mi&gt;&lt;mrow&gt;&lt;mo&gt;(&lt;/mo&gt;&lt;mi&gt;ℓ&lt;/mi&gt;&lt;mo&gt;+&lt;/mo&gt;&lt;mo&gt;log&lt;/mo&gt;&lt;mi&gt;m&lt;/mi&gt;&lt;mo&gt;)&lt;/mo&gt;&lt;/mrow&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt;). The asymptotic gate-count of the circuit is &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;Θ&lt;/mi&gt;&lt;mrow&gt;&lt;mo&gt;(&lt;/mo&gt;&lt;mrow&gt;&lt;mo&gt;(&lt;/mo&gt;&lt;mi&gt;m&lt;/mi&gt;&lt;mo&gt;+&lt;/mo&gt;&lt;mi&gt;f&lt;/mi&gt;&lt;mo&gt;)&lt;/mo&gt;&lt;/mrow&gt;&lt;mi&gt;⋅&lt;/mi&gt;&lt;mo&gt;lg&lt;/mo&gt;&lt;mi&gt;m&lt;/mi&gt;&lt;mo&gt;+&lt;/mo&gt;&lt;mi&gt;f&lt;/mi&gt;&lt;mi&gt;⋅&lt;/mi&gt;&lt;mi&gt;ℓ&lt;/mi&gt;&lt;mo&gt;)&lt;/mo&gt;&lt;/mrow&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt;. The asymptotic delay is &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;Θ&lt;/mi&gt;&lt;mrow&gt;&lt;mo&gt;(&lt;/mo&gt;&lt;mo&gt;lg&lt;/mo&gt;&lt;mi&gt;m&lt;/mi&gt;&lt;mo&gt;+&lt;/mo&gt;&lt;mo&gt;lg&lt;/mo&gt;&lt;mi&gt;f&lt;/mi&gt;&lt;mo&gt;+&lt;/mo&gt;&lt;mo&gt;lg&lt;/mo&gt;&lt;mi&gt;ℓ&lt;/mi&gt;&lt;mo&gt;)&lt;/mo&gt;&lt;/mrow&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt;&lt;span&gt;. We implemented our design on an FPGA with four combinations of parameters in which the FE-encoding fits in 512 or 1024 bits.&lt;/span&gt;&lt;/p&gt;&lt;p&gt;We present the first hardware design for a dynamic filter that maintains a set subject to insertions, deletions, and approximate membership queries. The design contains four main blocks: two memory banks that store FE-encodings and two combinational circuits for FE-encoding. Additional logic deals with double buffering and forwarding.&lt;/p&gt;&lt;p&gt;We implemented the dynamic filter on an FPGA with the following parameters: (1) Elements in the dataset are 32-bit strings. (2) The supported dataset can contain up to &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;msub&gt;&lt;mrow&gt;&lt;mi&gt;n&lt;/mi&gt;&lt;/mrow&gt;&lt;mrow&gt;&lt;mi&gt;m&lt;/mi&gt;&lt;mi&gt;a&lt;/mi&gt;&lt;mi&gt;x&lt;/mi&gt;&lt;/mrow&gt;&lt;/msub&gt;&lt;mo&gt;=&lt;/mo&gt;&lt;mn&gt;45&lt;/mn&gt;&lt;mi&gt;⋅&lt;/mi&gt;&lt;msup&gt;&lt;mrow&gt;&lt;mn&gt;2&lt;/mn&gt;&lt;/mrow&gt;&lt;mrow&gt;&lt;mn&gt;14&lt;/mn&gt;&lt;/mrow&gt;&lt;/msup&gt;&lt;mo&gt;=&lt;/mo&gt;&lt;mn&gt;737&lt;/mn&gt;&lt;mo&gt;,&lt;/mo&gt;&lt;mn&gt;280&lt;/mn&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt; elements. (3) The latency is 2-4 clock cycles. (4) Fixed (i.e., constant and stable) throughput. A new operation can be issued &lt;em&gt;every&lt;/em&gt; clock cycle. (5) We prove that the probability of a false-positive error is bounded by &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mn&gt;0&lt;/mn&gt;&lt;mo&gt;.&lt;/mo&gt;&lt;mn&gt;385&lt;/mn&gt;&lt;mi&gt;⋅&lt;/mi&gt;&lt;mn&gt;1&lt;/mn&gt;&lt;msup&gt;&lt;mrow&gt;&lt;mn&gt;0&lt;/mn&gt;&lt;/mrow&gt;&lt;mrow&gt;&lt;mo&gt;−&lt;/mo&gt;&lt;mn&gt;2&lt;/mn&gt;&lt;/mrow&gt;&lt;/msup&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt;. (6) We prove that the expected number of insertion failures is less than 1 for every 75 million insertions.&lt;/p&gt;&lt;p&gt;Synthesis of our filter on a Xilinx Alveo U250 FPGA achieves a clock rate of 100 MHz (the critical path is due to the memory access). We measure a fixed throughput of 97.7 million operations per second (the loss of 2.3% in the throughput is due to instabilities in the bandwidth of the AXI4 Lite I/O channel).&lt;/p&gt;&lt;p&gt;A unique feature of our filter implementation is that the throughput is stable and constant for all benchmarks and loads","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"105 ","pages":"Article 104992"},"PeriodicalIF":2.6,"publicationDate":"2024-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139094371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"H2-RAID: Improving the reliability of SSD RAID with unified SSD and HDD hybrid architecture","authors":"Jiarong Liu ,&nbsp;Tianyu Wang ,&nbsp;Xiaowei Chen ,&nbsp;Chao Li ,&nbsp;Zhaoyan Shen ,&nbsp;Zhiyong Zhang","doi":"10.1016/j.micpro.2023.104993","DOIUrl":"10.1016/j.micpro.2023.104993","url":null,"abstract":"<div><p><span>With the increasing development of SSD (Solid-State Drives) technology, SSD RAID (Redundant Arrays of Independent Disks) has been widely deployed in enterprise data centers. However, the inherent write endurance issue of SSD seriously affects the reliability of the array. Meanwhile, compared with conventional HDD-based RAID, SSD RAID exhibits very different failure characteristics, such as correlated failure (Balakrishnan et al., 2010) under RAID-5. In this paper, we present a Hybrid High reliability RAID architecture, named H</span><span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span>-RAID, by equipping each SSD with an extra HDD as the backup to improve the reliability of SSD RAID. Considering the relatively longer write latency of HDD, in H<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span><span><span>-RAID, we first propose an HDD-aware backup mechanism to smartly aggregate random writes into sequential writes to decrease performance degradation. In addition, to cope with the scenarios of SSD failure, an HDD-aware reconstruction method is further proposed to guarantee the reliability and the online </span>transaction processing performance. We build a novel Markov process-based mathematical model to analyze the reliability of different architectures, and the theoretical results prove the reliability of H</span><span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span>-RAID is much higher than that of traditional SSD RAID. To more accurately evaluate the performance influence of HDD on H<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span>-RAID, we develop a simulator based on Disksim and the experimental results show H<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span>-RAID significantly increases the reliability compared with SSD array (under RAID-5) while with little performance loss on average.</p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"105 ","pages":"Article 104993"},"PeriodicalIF":2.6,"publicationDate":"2023-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139062361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Retraction notice to “Intelligent control for new topological structure of Z-Source inverter based on ARM” [Microprocessors and Microsystems 81 (2021) 103735]","authors":"Hailong Liu ,&nbsp;Jiaona Chen","doi":"10.1016/j.micpro.2023.105001","DOIUrl":"https://doi.org/10.1016/j.micpro.2023.105001","url":null,"abstract":"","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 105001"},"PeriodicalIF":2.6,"publicationDate":"2023-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0141933123002466/pdfft?md5=0609f75249c060e3be3bd684835e1c24&pid=1-s2.0-S0141933123002466-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139100254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Retraction notice to “Searching and Learning English Translation Long Text Information Based on Heterogeneous Multiprocessors and Data Mining” [Microprocessors and Microsystems 82 (2021) 103895]","authors":"Xiaoping Shen,&nbsp;Runjuan Qin","doi":"10.1016/j.micpro.2023.104999","DOIUrl":"https://doi.org/10.1016/j.micpro.2023.104999","url":null,"abstract":"","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 104999"},"PeriodicalIF":2.6,"publicationDate":"2023-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0141933123002442/pdfft?md5=e878bdc42c9bd28074183cabcdcab06f&pid=1-s2.0-S0141933123002442-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139099688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Retraction notice to “An Improved Multilayer Perceptron Approach for Detecting Sugarcane Yield Production in IoT based Smart Agriculture” [Microprocessors and Microsystems 82 (2021) 103822]","authors":"Pengwen Wang ,&nbsp;Behzad Aalipur Hafshejani ,&nbsp;Daluyo Wang","doi":"10.1016/j.micpro.2023.105002","DOIUrl":"10.1016/j.micpro.2023.105002","url":null,"abstract":"","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 105002"},"PeriodicalIF":2.6,"publicationDate":"2023-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0141933123002478/pdfft?md5=1d09b24d1f85f13f20bcd14dc9cd77a4&pid=1-s2.0-S0141933123002478-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139094315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Retraction notice to ‘Medical IoT system platform and elderly patients’ femoral shaft fracture nursing’","authors":"Weiwei Liu,&nbsp;Kun Yao","doi":"10.1016/j.micpro.2023.105004","DOIUrl":"10.1016/j.micpro.2023.105004","url":null,"abstract":"","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 105004"},"PeriodicalIF":2.6,"publicationDate":"2023-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0141933123002491/pdfft?md5=4b24478650f7a103359f3b3a08717ac5&pid=1-s2.0-S0141933123002491-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139096712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Retraction notice to “Design of Embedded Digital Image Processing System Based on Zynq” [Microprocessors and Microsystems 83 (2021) 104005]","authors":"Jin Liu ,&nbsp;Jie Feng","doi":"10.1016/j.micpro.2023.105000","DOIUrl":"https://doi.org/10.1016/j.micpro.2023.105000","url":null,"abstract":"","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 105000"},"PeriodicalIF":2.6,"publicationDate":"2023-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0141933123002454/pdfft?md5=fc43d609d3947e2d3675906cbcfae5c8&pid=1-s2.0-S0141933123002454-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139099687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}