Microprocessors and Microsystems最新文献_第8页

Indoor localization using device sensors: A threat to privacy 使用设备传感器进行室内定位：对隐私的威胁

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-03-06 DOI: 10.1016/j.micpro.2024.105041

Hitesh Verma , Smita Naval , Balaprakasa Rao Killi , Vinod P.

{"title":"Indoor localization using device sensors: A threat to privacy","authors":"Hitesh Verma , Smita Naval , Balaprakasa Rao Killi , Vinod P.","doi":"10.1016/j.micpro.2024.105041","DOIUrl":"10.1016/j.micpro.2024.105041","url":null,"abstract":"<div><p>The localization techniques used in today’s smartphone are mainly based on Global Positioning System (GPS). However, GPS Sensors cannot work properly under in-door and underground locations. Therefore, many applications utilize device sensors such as accelerometer, gyrometer, and magnetometer for indoor localization. In this paper, we present a misuse case of how device sensors can be used to exploit the privacy of a user by geo-tracking. We propose an attack model through which the user location can be compromised without using the GPS sensors. The proposed attack model comprises of two stages. The first stage consists of deployment of the malicious application on the users’ smart-phones and gathering the information of various sensors in the background. The collected sensor data is uploaded to the malicious cloud server set up by the adversary. The second stage consists of pre-processing the sensor data received from the malicious cloud server and plot the user’s trajectory onto a graph in real-time. The proposed attack model is evaluated by developing two applications. The victim application tracks location, direction, and trajectory of the user without any location permission from the user. The proposed model achieves an accuracy of 98% without using special infrastructure and separate training phase. Further, we have discussed three mitigation schemes, which can be adapted by the Android developers in order to protect the user’s privacy.</p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"106 ","pages":"Article 105041"},"PeriodicalIF":2.6,"publicationDate":"2024-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140087111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Retraction notice to the articles published in the Special issue Smart Agri from “Microprocessors and Microsystems” 关于 "微处理器与微系统 "特刊《智能农业》中发表文章的撤稿通知

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-02-28 DOI: 10.1016/j.micpro.2024.105038

引用次数: 0

A light-weight neuromorphic controlling clock gating based multi-core cryptography platform 基于时钟门控的轻量级神经形态多核加密平台

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-02-26 DOI: 10.1016/j.micpro.2024.105040

Pham-Khoi Dong , Khanh N. Dang , Duy-Anh Nguyen , Xuan-Tu Tran

{"title":"A light-weight neuromorphic controlling clock gating based multi-core cryptography platform","authors":"Pham-Khoi Dong , Khanh N. Dang , Duy-Anh Nguyen , Xuan-Tu Tran","doi":"10.1016/j.micpro.2024.105040","DOIUrl":"10.1016/j.micpro.2024.105040","url":null,"abstract":"<div><p>While speeding up cryptography tasks can be accomplished by using a multi-core architecture to parallelize computation, one of the major challenges is optimizing power consumption. In principle, depending on the computation workload, individual cores can be turned off to save power during operation. However, too few active cores may lead to computational bottlenecks. In this work, we propose a novel platform named Spike-MCryptCores: a low-power multi-core AES platform with a neuromorphic controller. The proposed Spike-MCryptCores platform is composed of multiple AES cores, each core is equipped with a clock-gating scheme for reducing its power consumption while being idle. To optimize the power consumption of the whole platform, we use a neuromorphic controller. Therefore, a comprehensive framework to generate a data set, train the neural network, and produce hardware configuration for the Spiking Neural Network (SNN), a brain-inspired computing paradigm, is also presented in this paper. Moreover, Spike-MCryptCores integrates the hardware SNN inside its architecture to support low-cost and low-latency adaptations. The results show that implemented SNN controller occupies only 2.3 % of the overall area cost while providing the ability to reduce power consumption significantly. The lightweight SNN controller model is trained and tested with up to 95 % accuracy. The maximum difference between the predicted number of cores and the ideal one from the label is one unit only. Under 24 test scenarios, a SNN controller with clock-gating helps Spike-MCryptCores reducing the power consumption by 48.6 % on the average; by 67 % for the best-case scenario, and by 39 % for the worst-case scenario.</p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"106 ","pages":"Article 105040"},"PeriodicalIF":2.6,"publicationDate":"2024-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139987897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

MOSAIC: Maximizing ResOurce Sharing in Behavioral Application SpecIfic ProCessors MOSAIC：最大限度地共享行为应用程序模拟处理器中的资源

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-02-20 DOI: 10.1016/j.micpro.2024.105039

Qilin Si, Benjamin Carrion Schafer

引用次数: 0

A Real-time P-SFA hardware implementation of Deep Neural Networks using FPGA 使用 FPGA 的深度神经网络实时 P-SFA 硬件实现

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-02-17 DOI: 10.1016/j.micpro.2024.105037

Nour Elshahawy , Sandy A. Wasif , Maggie Mashaly , Eman Azab

{"title":"A Real-time P-SFA hardware implementation of Deep Neural Networks using FPGA","authors":"Nour Elshahawy , Sandy A. Wasif , Maggie Mashaly , Eman Azab","doi":"10.1016/j.micpro.2024.105037","DOIUrl":"10.1016/j.micpro.2024.105037","url":null,"abstract":"<div><p>Machine Learning (ML) algorithms, specifically Artificial Neural Networks (ANNs), have proved their effectiveness in solving complex problems in many different applications and multiple fields. This paper focuses on optimizing the activation function (AF) block of the NN hardware architecture. The AF block used is based on a probability-based sigmoid function approximation block (P-SFA) combined with a novel real-time probability module (PRT) that calculates the probability of the input data. The proposed NN design aims to use the least amount of hardware resources and area while maintaining a high recognition accuracy. The proposed AF module in this work consists of two P-SFA blocks and the PRT component. The architecture proposed for implementing NNs is evaluated on Field Programmable Gate Arrays (FPGAs). The proposed design has achieved a recognition accuracy of 97.84 % on a 6-layer Deep Neural Network (DNN) for the MNIST dataset and a recognition accuracy of 88.58% on a 6-layer DNN for the FMNIST dataset. The proposed AF module has a total area of 1136 LUTs and 327 FFs, a logical critical path delay of 8.853 ns. The power consumption of the P-SFA block is 6 mW and the PRT block is 5 mW.</p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"106 ","pages":"Article 105037"},"PeriodicalIF":2.6,"publicationDate":"2024-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139919876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and evaluation of low power and area efficient approximate Booth multipliers for error tolerant applications 设计和评估用于容错应用的低功耗、高效面积近似布斯乘法器

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-02-17 DOI: 10.1016/j.micpro.2024.105036

Vishal Gundavarapu , P. Gowtham , A. Anita Angeline , P. Sasipriya

{"title":"Design and evaluation of low power and area efficient approximate Booth multipliers for error tolerant applications","authors":"Vishal Gundavarapu , P. Gowtham , A. Anita Angeline , P. Sasipriya","doi":"10.1016/j.micpro.2024.105036","DOIUrl":"https://doi.org/10.1016/j.micpro.2024.105036","url":null,"abstract":"<div><p>Approximate computing is an innovative design methodology to reduce the design complexity with an improvement in power efficiency, performance and area by compromising on the requirement of accuracy. In this paper, 8-bit approximate Booth multipliers have been proposed based on the approximate Radix-4 modified Booth encoding algorithm and approximate compressors for partial product accumulation to produce the final products are proposed. Two approximate Probability Based Booth Encoders (PBBE-1 and PBBE-2) have been proposed and used in the Booth multipliers. Error parameters have been measured and compared with the existing approximate booth multipliers. Exact booth multiplier of novel design existing in the literature has also been implemented for comparison purpose. The proposed approximate multipliers are then used in applications like image multiplication and IIR bi-quad filtering to prove their performance. Simulation results prove that the proposed booth multipliers outperform the existing approximate booth multipliers in terms of power and area with better accuracy. Synthesis results prove that the proposed Multiplier 6 was found to be the most efficient with a 56 % power consumption improvement and a 47 % area improvement when compared to the exact multiplier. All the simulations are carried out using Cadence® Genus with 180 nm CMOS process technology.</p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"106 ","pages":"Article 105036"},"PeriodicalIF":2.6,"publicationDate":"2024-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139908537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Retraction notice to “FPGA implementation of low power and high speed image edge detection algorithm” [Microprocessors and Microsystems 75, 2020, 103053] 关于 "低功耗和高速图像边缘检测算法的 FPGA 实现 "的撤稿通知 [Microprocessors and Microsystems 75, 2020, 103053]

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-02-14 DOI: 10.1016/j.micpro.2024.105024

R. Menaka , R. Janarthanan , K. Deeba

引用次数: 0

Retraction notice to 'A machine learning based IoT for providing an intrusion detection system for security' [Microprocessors and Microsystems 82 (2021) 103741] 基于机器学习的物联网为安全提供入侵检测系统 "的撤稿通知 [Microprocessors and Microsystems 82 (2021) 103741]

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-02-14 DOI: 10.1016/j.micpro.2024.105028

Dhanke Jyoti Atul , R. Kamalraj , G. Ramesh , K. Sakthidasan Sankaran , Sudhir Sharma , Syed Khasim

引用次数: 0

Retraction notice to ‘Virtual garden landscape planning based on FPGA and GIS platform’ [Microprocessors and Microsystems 79 (2020) 103314] 基于 FPGA 和 GIS 平台的虚拟园林景观规划"[Microprocessors and Microsystems 79 (2020) 103314] 撤稿通知

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-02-14 DOI: 10.1016/j.micpro.2024.105025

Xiaoxia Bai

引用次数: 0

Retraction notice to 'An Improved Dynamic Process Neural Network Prediction Model Identification Method' [Microprocessors and Microsystems 80 (2021) 103573] 改进的动态过程神经网络预测模型识别方法》的撤稿通知 [Microprocessors and Microsystems 80 (2021) 103573]

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2024-02-14 DOI: 10.1016/j.micpro.2024.105026

Shuran Lyu , Peng Liu , Lu Liu , Shuqi Ma , Tao Wang

引用次数: 0