MOSAIC:最大限度地共享行为应用程序模拟处理器中的资源

IF 1.9 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Qilin Si, Benjamin Carrion Schafer
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引用次数: 0

摘要

这项工作提出了一种方法,可以快速确定哪些硬件加速器(HWaccs)应一起映射到特定应用指令集处理器(ASIP)上,从而使它们之间共享的资源最大化。这项工作特别针对从用于高级合成(HLS)的未计时行为描述中生成的 HWaccs。虽然 HLS 是一种单进程合成方法,但我们的方法能够根据 HWaccs 的资源共享潜力,将它们的行为描述合并为单一描述,从而强制它们共享资源。这些共享资源包括乘法器、加法器、除法器等功能单元(FU)以及寄存器。特别是,我们提出的流程可节省高达 48% 的面积,平均节省 30%。由于穷举所有可能的组合会导致较长的运行时间,因此我们提出了一种快速启发式方法,其结果与之相当(平均只差 6%),同时速度更快(平均 500 倍)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
MOSAIC: Maximizing ResOurce Sharing in Behavioral Application SpecIfic ProCessors

This work presents a method that can quickly determine which hardware accelerators (HWaccs) should be mapped together onto an Application-Specific Instruction Set Processor (ASIP), such that the resources shared among them are maximized. This work in particular targets HWaccs generated from untimed behavioral descriptions for High-Level Synthesis (HLS). Although HLS is a single process synthesis method, our approach is able to force resource sharing among the HWaccs by combining their behavioral descriptions together into a single description based on their potential to share resources. These shared resources include functional units (FUs) like multipliers, adders, and dividers, and also registers. In particular, our proposed flow leads up to 48% in area savings and on average 30%. Because an exhaustive enumeration of all possible combinations can lead to long runtimes, we propose a fast heuristic that leads to comparable results (only 6% worse on average), while being much faster (on average 500×).

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来源期刊
Microprocessors and Microsystems
Microprocessors and Microsystems 工程技术-工程:电子与电气
CiteScore
6.90
自引率
3.80%
发文量
204
审稿时长
172 days
期刊介绍: Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) is a journal covering all design and architectural aspects related to embedded systems hardware. This includes different embedded system hardware platforms ranging from custom hardware via reconfigurable systems and application specific processors to general purpose embedded processors. Special emphasis is put on novel complex embedded architectures, such as systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC) and multi-processor systems on a chip (MPSoC), as well as, their memory and communication methods and structures, such as network-on-chip (NoC). Design automation of such systems including methodologies, techniques, flows and tools for their design, as well as, novel designs of hardware components fall within the scope of this journal. Novel cyber-physical applications that use embedded systems are also central in this journal. While software is not in the main focus of this journal, methods of hardware/software co-design, as well as, application restructuring and mapping to embedded hardware platforms, that consider interplay between software and hardware components with emphasis on hardware, are also in the journal scope.
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