A light-weight neuromorphic controlling clock gating based multi-core cryptography platform

IF 1.9 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Pham-Khoi Dong , Khanh N. Dang , Duy-Anh Nguyen , Xuan-Tu Tran
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Abstract

While speeding up cryptography tasks can be accomplished by using a multi-core architecture to parallelize computation, one of the major challenges is optimizing power consumption. In principle, depending on the computation workload, individual cores can be turned off to save power during operation. However, too few active cores may lead to computational bottlenecks. In this work, we propose a novel platform named Spike-MCryptCores: a low-power multi-core AES platform with a neuromorphic controller. The proposed Spike-MCryptCores platform is composed of multiple AES cores, each core is equipped with a clock-gating scheme for reducing its power consumption while being idle. To optimize the power consumption of the whole platform, we use a neuromorphic controller. Therefore, a comprehensive framework to generate a data set, train the neural network, and produce hardware configuration for the Spiking Neural Network (SNN), a brain-inspired computing paradigm, is also presented in this paper. Moreover, Spike-MCryptCores integrates the hardware SNN inside its architecture to support low-cost and low-latency adaptations. The results show that implemented SNN controller occupies only 2.3 % of the overall area cost while providing the ability to reduce power consumption significantly. The lightweight SNN controller model is trained and tested with up to 95 % accuracy. The maximum difference between the predicted number of cores and the ideal one from the label is one unit only. Under 24 test scenarios, a SNN controller with clock-gating helps Spike-MCryptCores reducing the power consumption by 48.6 % on the average; by 67 % for the best-case scenario, and by 39 % for the worst-case scenario.

基于时钟门控的轻量级神经形态多核加密平台
虽然利用多核架构并行计算可以加快密码学任务的速度,但其中一个主要挑战是优化功耗。原则上,根据计算工作量,可以在运行期间关闭单个内核以节省功耗。然而,过少的活动内核可能会导致计算瓶颈。在这项工作中,我们提出了一种名为 Spike-MCryptCores 的新型平台:一种带有神经形态控制器的低功耗多核 AES 平台。所提出的 Spike-MCryptCores 平台由多个 AES 内核组成,每个内核都配备了时钟门方案,以降低空闲时的功耗。为了优化整个平台的功耗,我们使用了神经形态控制器。因此,本文还提出了一个综合框架,用于生成数据集、训练神经网络,以及为尖峰神经网络(SNN)(一种大脑启发计算范例)生成硬件配置。此外,Spike-MCryptCores 还在其架构中集成了硬件 SNN,以支持低成本和低延迟的自适应。研究结果表明,实现的 SNN 控制器仅占整体面积成本的 2.3%,同时还能显著降低功耗。轻量级 SNN 控制器模型经过训练和测试,准确率高达 95%。根据标签预测的内核数与理想内核数之间的最大差异仅为一个单位。在 24 种测试场景下,带有时钟门的 SNN 控制器帮助 Spike-MCryptCores 平均降低了 48.6% 的功耗;在最佳场景下降低了 67%,在最差场景下降低了 39%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
Microprocessors and Microsystems
Microprocessors and Microsystems 工程技术-工程:电子与电气
CiteScore
6.90
自引率
3.80%
发文量
204
审稿时长
172 days
期刊介绍: Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) is a journal covering all design and architectural aspects related to embedded systems hardware. This includes different embedded system hardware platforms ranging from custom hardware via reconfigurable systems and application specific processors to general purpose embedded processors. Special emphasis is put on novel complex embedded architectures, such as systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC) and multi-processor systems on a chip (MPSoC), as well as, their memory and communication methods and structures, such as network-on-chip (NoC). Design automation of such systems including methodologies, techniques, flows and tools for their design, as well as, novel designs of hardware components fall within the scope of this journal. Novel cyber-physical applications that use embedded systems are also central in this journal. While software is not in the main focus of this journal, methods of hardware/software co-design, as well as, application restructuring and mapping to embedded hardware platforms, that consider interplay between software and hardware components with emphasis on hardware, are also in the journal scope.
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