Microprocessors and Microsystems最新文献_第4页

Analog to digital memory modeling for test 模拟到数字存储器建模测试

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2025-11-01 Epub Date: 2025-08-19 DOI: 10.1016/j.micpro.2025.105189

Dorian Ronga , Gianmarco Mongelli , Eric Faehn , Patrick Girard , Arnaud Virazel

{"title":"Analog to digital memory modeling for test","authors":"Dorian Ronga , Gianmarco Mongelli , Eric Faehn , Patrick Girard , Arnaud Virazel","doi":"10.1016/j.micpro.2025.105189","DOIUrl":"10.1016/j.micpro.2025.105189","url":null,"abstract":"<div><div>Memory testing is crucial as memories play an ever-increasing important role in modern computing systems, to which a memory malfunction can lead to a system failure. Memory testing is commonly addressed by a functional testing approach that consists in verifying the manufactured memory function. Functional testing focuses on identifying memory functional failure mechanisms, which are modeled by Functional Fault Models (FFM), and for which dedicated test algorithms are developed to ensure their detection. However, as technology shrinks, fault mechanisms in memories become more complex, as well as their detection conditions. To anticipate any limitation, memory structural testing is investigated. Structural testing proposes to study the defect before the fault, as one or several manufactured defects or imperfections may be responsible for a fault. A structural test methodology for memory has been recently published and proposes to adapt the Cell-Aware test methodology from the digital domain to analog memories. As the resulting Structural Fault Models (SFM) for analog memory are compatible with digital test environment, this work proposes a digital SRAM modeling methodology, compatible with digital simulation and test environments, leveraging Fault Simulator for test algorithm coverage analysis, and Automatic Test Pattern Generator for dedicated and optimized defect-specific test generation.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"118 ","pages":"Article 105189"},"PeriodicalIF":2.6,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A cost-effective fault-tolerant EDAC solution for SRAM-based FPGAs and memory in space applications 为空间应用中基于sram的fpga和存储器提供经济高效的容错EDAC解决方案

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2025-11-01 Epub Date: 2025-10-05 DOI: 10.1016/j.micpro.2025.105208

Youcef Bentoutou, El Habib Bensikaddour, Chahira Serief, Chafika Belamri, Malika Bendouda

{"title":"A cost-effective fault-tolerant EDAC solution for SRAM-based FPGAs and memory in space applications","authors":"Youcef Bentoutou, El Habib Bensikaddour, Chahira Serief, Chafika Belamri, Malika Bendouda","doi":"10.1016/j.micpro.2025.105208","DOIUrl":"10.1016/j.micpro.2025.105208","url":null,"abstract":"<div><div>The reliability of memory and Field Programmable Gate Array (FPGA) devices in space is significantly challenged by Single Event Upsets (SEUs) caused by radiation exposure. To mitigate this, traditional methods such as Hamming (12, 8) codes and Triple Modular Redundancy (TMR) are commonly used. TMR involves triplicating memory or FPGA devices and using a voting logic to detect and correct erroneous bits, offering defense against radiation-induced upsets. However, this approach comes at a high cost in terms of resource utilization and power consumption. This paper presents a novel Error Detection and Correction (EDAC) system that combines partial TMR and Quasi-cyclic (QC) codes to enhance the protection of memory and SRAM-based FPGAs. The system selectively applies partial TMR to critical design components, reducing overhead while ensuring robust SEU protection. QC codes further improve memory error correction capabilities while minimizing the overhead associated with TMR. Experimental results demonstrate that the proposed EDAC system outperforms traditional methods, offering notable reductions in delay, area, and power consumption. This approach provides a more efficient and cost-effective solution for space applications, ensuring better reliability of FPGA and memory devices in low-Earth polar orbits.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"118 ","pages":"Article 105208"},"PeriodicalIF":2.6,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145267170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Evaluating the performance of TinyML singular and ensemble techniques for intrusion detection in IoT networks 评估TinyML奇异和集成技术在物联网网络中入侵检测的性能

IF 1.9 4区计算机科学

Microprocessors and Microsystems Pub Date : 2025-09-01 Epub Date: 2025-06-03 DOI: 10.1016/j.micpro.2025.105172

Abderahmane Hamdouchi , Ali Idri

{"title":"Evaluating the performance of TinyML singular and ensemble techniques for intrusion detection in IoT networks","authors":"Abderahmane Hamdouchi , Ali Idri","doi":"10.1016/j.micpro.2025.105172","DOIUrl":"10.1016/j.micpro.2025.105172","url":null,"abstract":"<div><div>As the Internet of Things (IoT) expands, safeguarding IoT networks from vulnerabilities becomes critical. Intrusion detection systems (IDS) leveraging machine learning (ML) techniques are essential for enhancing security and preventing unauthorized access. However, transmitting data to the cloud can introduce latency, impeding real-time attack detection. This research evaluates three TinyML ensemble techniques (random forest, XGBoost, and extra trees) and three singular techniques (decision tree, Gaussian naive Bayes, and multilayer perceptron) using two feature selection methods (maximum relevance minimum redundancy and analysis of variance) on the NF-ToN-IoT-v2 and NF-BoT-IoT-v2 datasets for cyberattack detection. Evaluations on the Arduino UNO used the prediction performance criteria (Cohen’s kappa and Matthew’s correlation coefficient), device metrics (latency, static RAM, and flash memory), and the Scott-Knott test and Borda count voting system to assess the statistical significance and to rank the models. Results show that singular TinyML models outperformed ensemble models for multiclass classification in the IDS-IoT context. The best models are: (1) MLP with 20 features and a hidden layer size of 56 for NF-ToN-IoT-v2; and (2) ET with 13 features, 2 estimators, and a tree depth of 16 for NF-BoT-IoT-v2.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"117 ","pages":"Article 105172"},"PeriodicalIF":1.9,"publicationDate":"2025-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144262850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

CRAX: Code reuse attacks on Xtensa’s register window ABI CRAX：对Xtensa的注册窗口ABI的代码重用攻击

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2025-09-01 Epub Date: 2025-08-12 DOI: 10.1016/j.micpro.2025.105188

Adebayo Omotosho , Christian Hammer

{"title":"CRAX: Code reuse attacks on Xtensa’s register window ABI","authors":"Adebayo Omotosho , Christian Hammer","doi":"10.1016/j.micpro.2025.105188","DOIUrl":"10.1016/j.micpro.2025.105188","url":null,"abstract":"<div><div>Code reuse attacks exploit existing codes in applications to hijack control flow and cause security breaches. However, reusing code on architectures with a register window or windowed register application binary interface (Winreg ABI), as known on Xtensa, poses significant challenges due to their unique architectural behavior. Winreg ABI aims to enhance register performance by reducing stack operations during procedure calls in reduced instruction set computer architectures. Rudimentary investigations have explored Winreg ABI exception handlers as potential sources of vulnerability in register window operations. Despite these efforts, the approach has been limited, even in synthetic examples, as it cannot technically reuse codes beyond changing register values.</div><div>In this paper, we present a novel approach to producing gadget-based code reuse attacks on Xtensa cores utilizing Winreg ABI, as found in embedded systems like ESP32 and ESP8266. At the same time, we showcase that established methods to detect such attacks such as leveraging hardware performance counter can also detect such attack schemes. Finally, we identify an additional potential loophole in the Winreg ABI. Our evaluation results using a number of benchmark applications demonstrate that successful attacks exhibit a consistent pattern that can be accurately detected.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"117 ","pages":"Article 105188"},"PeriodicalIF":2.6,"publicationDate":"2025-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144858203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Implementation and characterization of a fault-tolerant CCSDS 123 hardware accelerator under neutron radiation 中子辐射容错CCSDS 123硬件加速器的实现与特性研究

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2025-09-01 Epub Date: 2025-07-30 DOI: 10.1016/j.micpro.2025.105184

Wesley Grignani , Douglas A. Santos , Maria Kastriotou , Carlo Cazzaniga , Luigi Dilillo , Douglas R. Melo

{"title":"Implementation and characterization of a fault-tolerant CCSDS 123 hardware accelerator under neutron radiation","authors":"Wesley Grignani , Douglas A. Santos , Maria Kastriotou , Carlo Cazzaniga , Luigi Dilillo , Douglas R. Melo","doi":"10.1016/j.micpro.2025.105184","DOIUrl":"10.1016/j.micpro.2025.105184","url":null,"abstract":"<div><div>In space applications, remote sensing relies on HSIs (Hyperspectral Images) to capture extensive Earth observation data. However, the substantial data volumes generated by HSIs present significant challenges for onboard storage and processing in space systems, underscoring the importance of efficient compression strategies. Additionally, the harsh conditions of the space environment expose these systems to potential faults, making the integration of fault-tolerant mechanisms crucial for maintaining reliable operation. In this context, this article presents the implementation of a low-cost and fault-tolerant CCSDS 123 HSI compressor. The compressor is present in different configurations employing hardening techniques such as TMR (Triple Modular Redundancy) and Hamming ECC (Error Correcting Code) to mitigate SEUs (Single-Event Upsets). We implemented techniques to enhance observability and evaluated the compressor reliability through fault injection simulations and physical tests at the ChipIr neutron irradiation facility. We present the resource utilization and performance results of each version with a comparative analysis with related work. The results highlight the lowest resource utilization achieved in the unhardened version, capable of processing 20.57 MSa/s and accelerating the application in 24<span><math><mo>×</mo></math></span> compared to a software solution. The reliability results demonstrate a high error rate of 97.9% in the unhardened version, significantly reduced in partially hardened versions, with no error propagation in the fully hardened design. Furthermore, we present an analysis of the main components of the accelerator affected by the radiation-induced events observed in the particle accelerator test.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"117 ","pages":"Article 105184"},"PeriodicalIF":2.6,"publicationDate":"2025-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144749623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Detecting time drifts for securing Proof of Hardware Time in blockchain 在区块链中检测时间漂移以确保硬件时间证明

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2025-09-01 Epub Date: 2025-08-06 DOI: 10.1016/j.micpro.2025.105185

Quentin Jayet , Christine Hennebert , Yann Kieffer , Vincent Beroulle

{"title":"Detecting time drifts for securing Proof of Hardware Time in blockchain","authors":"Quentin Jayet , Christine Hennebert , Yann Kieffer , Vincent Beroulle","doi":"10.1016/j.micpro.2025.105185","DOIUrl":"10.1016/j.micpro.2025.105185","url":null,"abstract":"<div><div>Blockchain technology enables the creation of a timestamped, shared, and replicated history of events among participants who do not trust each other. To agree on the shared history, the blockchain uses a consensus protocol, such as Nakamoto’s protocol in Bitcoin. This protocol relies on a proof that statistically ensures the elapsed time between two blocks by design through the Proof of Work (PoW) mechanism. However, PoW relies heavily on computation and is not suitable for embedded systems. Proof of Hardware Time (PoHT) aims to provide a secure by design elapsed time proof mechanism with low power consumption. PoHT is embedded in a System on Module (SoM) that features an ARM Cortex-A7 microprocessor with a TrustZone and a Trusted Platform Module. This paper focuses on the security of the elapsed time measurement during PoHT, conducting experimental attacks targeting clock oscillators under temperature variations. It presents a consolidation of the various available time sources, as well as a solution for detecting time drifts. Furthermore, an embedded architecture for the time drift detection system is outlined and experimental testing of the system is performed.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"117 ","pages":"Article 105185"},"PeriodicalIF":2.6,"publicationDate":"2025-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144831442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High throughput DLP and mixed radix based architectures of Viterbi decoder 高吞吐量DLP和基于混合基数的维特比解码器架构

IF 1.9 4区计算机科学

Microprocessors and Microsystems Pub Date : 2025-09-01 Epub Date: 2025-06-23 DOI: 10.1016/j.micpro.2025.105181

Mohamed Asan Basiri M.

{"title":"High throughput DLP and mixed radix based architectures of Viterbi decoder","authors":"Mohamed Asan Basiri M.","doi":"10.1016/j.micpro.2025.105181","DOIUrl":"10.1016/j.micpro.2025.105181","url":null,"abstract":"<div><div>Viterbi decoders play an important role in digital communication. This manuscript proposes two high throughput VLSI architectures of Viterbi decoder. In the first proposed architecture, the data level parallelism (DLP) based Viterbi decoder of rate <span><math><mfrac><mrow><mn>1</mn></mrow><mrow><mi>N</mi></mrow></mfrac></math></span> can be used to perform 1, 2, 4, 8, …parallel decodings of rates <span><math><mfrac><mrow><mn>1</mn></mrow><mrow><mi>N</mi></mrow></mfrac></math></span>, <span><math><mfrac><mrow><mn>1</mn></mrow><mrow><mrow><mo>(</mo><mi>N</mi><mo>/</mo><mn>2</mn><mo>)</mo></mrow></mrow></mfrac></math></span>, <span><math><mfrac><mrow><mn>1</mn></mrow><mrow><mrow><mo>(</mo><mi>N</mi><mo>/</mo><mn>4</mn><mo>)</mo></mrow></mrow></mfrac></math></span>, <span><math><mfrac><mrow><mn>1</mn></mrow><mrow><mrow><mo>(</mo><mi>N</mi><mo>/</mo><mn>8</mn><mo>)</mo></mrow></mrow></mfrac></math></span>, …respectively. The second proposed mixed radix Viterbi decoder architecture is to perform four numbers of radix-<span><math><msup><mrow><mn>2</mn></mrow><mrow><mi>k</mi><mo>−</mo><mn>1</mn></mrow></msup></math></span> decodings in parallel using one radix-<span><math><msup><mrow><mn>2</mn></mrow><mrow><mi>k</mi></mrow></msup></math></span> Viterbi decoder, where <span><math><mrow><mi>k</mi><mo>≥</mo><mn>1</mn></mrow></math></span>. All the conventional and proposed Viterbi decoders are implemented in 45 nm CMOS technology using Cadence. The synthesis results show that the proposed designs achieve high throughput as compared with the conventional designs. According to the synthesis results, the proposed mixed radix-2&4 decoder achieves 73.9% of improvement in maximum throughput as compared with the conventional radix-4 design.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"117 ","pages":"Article 105181"},"PeriodicalIF":1.9,"publicationDate":"2025-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144471309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High throughput event filtering: The interpolation-based DIF algorithm hardware architecture 高吞吐量事件过滤：基于插值的DIF算法硬件架构

IF 1.9 4区计算机科学

Microprocessors and Microsystems Pub Date : 2025-09-01 Epub Date: 2025-06-11 DOI: 10.1016/j.micpro.2025.105171

Marcin Kowalczyk, Tomasz Kryjak

{"title":"High throughput event filtering: The interpolation-based DIF algorithm hardware architecture","authors":"Marcin Kowalczyk, Tomasz Kryjak","doi":"10.1016/j.micpro.2025.105171","DOIUrl":"10.1016/j.micpro.2025.105171","url":null,"abstract":"<div><div>In recent years, there has been rapid development in the field of event vision. It manifests itself both on the technical side, as better and better event sensors are available, and on the algorithmic side, as more and more applications of this technology are proposed and scientific papers are published. However, the data stream from these sensors typically contains a significant amount of noise, which varies depending on factors such as the degree of illumination in the observed scene or the temperature of the sensor. We propose a hardware architecture of the Distance-based Interpolation with Frequency Weights(DIF) filter and implement it on an FPGA chip. To evaluate the algorithm and compare it with other solutions, we have prepared a new high-resolution event dataset, which we are also releasing to the community. Our architecture achieved a throughput of 403.39 million events per second (MEPS) for a sensor resolution of 1280 × 720 and 428.45 MEPS for a resolution of 640 × 480. The averagevalues of the Area Under the Receiver Operating Characteristic (AUROC) index ranged from 0.844 to 0.999, depending on the dataset, which is comparable to the state-of-the-art filtering solutions, but with much higher throughput and better operation over a wide range of noise levels.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"117 ","pages":"Article 105171"},"PeriodicalIF":1.9,"publicationDate":"2025-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144502646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Real-time neural network-based thermal stress compensation for pressure sensors in precision localization systems 基于实时神经网络的精密定位系统压力传感器热应力补偿

IF 1.9 4区计算机科学

Microprocessors and Microsystems Pub Date : 2025-09-01 Epub Date: 2025-07-07 DOI: 10.1016/j.micpro.2025.105183

Paola Vitolo , Rosalba Liguori , Luigi Di Benedetto , Alfredo Rubino , Danilo Pau , Gian Domenico Licciardo

{"title":"Real-time neural network-based thermal stress compensation for pressure sensors in precision localization systems","authors":"Paola Vitolo , Rosalba Liguori , Luigi Di Benedetto , Alfredo Rubino , Danilo Pau , Gian Domenico Licciardo","doi":"10.1016/j.micpro.2025.105183","DOIUrl":"10.1016/j.micpro.2025.105183","url":null,"abstract":"<div><div>This article presents a real-time Artificial Intelligence-based Reconfigurable Self-Calibration Unit (AI-ReSCU) for piezoresistive MEMS pressure sensors, designed to mitigate long-term drift effects induced by thermal stress. The system integrates a compact and reconfigurable neural network to dynamically estimate and correct sensor inaccuracies with minimal energy and area overhead. The architecture comprises a trigger module for detecting deviations from nominal behavior and a compensation engine driven by a quantized neural network optimized for hardware efficiency. The network processes temporal input windows and operates using 24-bit activations and 1-bit weights, enabling real-time inference with ultra-low power consumption. The fully digital system was prototyped in STMicroelectronics’ BCD8 technology, occupying 0.55 mm<sup>2</sup> and achieving a dynamic power consumption of 4.46 nW under typical conditions, thanks to extensive resource reuse and clock gating strategies. Offline experimental validation on LPS22HH pressure sensors demonstrated the system’s ability to recover up to 1.6 hPa of drift-induced error with a recovery latency of approximately 50 input samples, while maintaining measurement deviations within ±0.5 hPa across multiple stress scenarios.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"117 ","pages":"Article 105183"},"PeriodicalIF":1.9,"publicationDate":"2025-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144633254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Scala defined hardware generators for Chisel Scala为Chisel定义了硬件生成器

IF 2.6 4区计算机科学

Microprocessors and Microsystems Pub Date : 2025-09-01 Epub Date: 2025-07-21 DOI: 10.1016/j.micpro.2025.105182

Martin Schoeberl , Hans Jakob Damsgaard , Luca Pezzarossa , Oliver Keszocze , Erling Rennemo Jellum , Scott Beamer

{"title":"Scala defined hardware generators for Chisel","authors":"Martin Schoeberl , Hans Jakob Damsgaard , Luca Pezzarossa , Oliver Keszocze , Erling Rennemo Jellum , Scott Beamer","doi":"10.1016/j.micpro.2025.105182","DOIUrl":"10.1016/j.micpro.2025.105182","url":null,"abstract":"<div><div>We describe digital hardware designs in hardware description languages such as VHDL and SystemVerilog. Both languages were developed in the 1980s and, although regularly updated, are still in the style of their time. They lack the constructs to write more configurable generators than just the number of bits for an operation. Based on Scala, Chisel is a hardware construction language that helps to write hardware generators.</div><div>Hardware generators are not a new idea. Scripting languages, such as Perl and TCL, are often used to generate VHDL or Verilog code from other sources of system description. However, mixing two languages and embedding VHDL or Verilog strings in generator code is not scalable.</div><div>As Chisel is embedded in Scala, we can write the generators using the same language/environment as we use to describe the digital logic. This paper explores different examples and patterns to describe parameterizable hardware generators. We are confident that practices from software development can improve the productivity of hardware designers to build and test the next billion transistor chips.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"117 ","pages":"Article 105182"},"PeriodicalIF":2.6,"publicationDate":"2025-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144722345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0