Algorithms for scheduling CNNs on multicore MCUs at the neuron and layer levels

IF 1.9 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Petr Dobiáš , Thomas Garbay , Bertrand Granado , Khalil Hachicha , Andrea Pinna
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引用次数: 0

Abstract

Convolutional neural networks (CNNs) are progressively deployed on embedded systems, which is challenging because their computational and energy requirements need to be satisfied by devices with limited resources and power supplies. For instance, they can be implemented in the Internet of Things or edge computing, i.e., in applications using low-power and low-performance microcontroller units (MCUs). Monocore MCUs are not tailored to respond to the computational and energy requirements of CNNs due to their limited resources, but a multicore MCU can overcome these limitations. This paper presents an empirical study analysing three algorithms for scheduling CNNs on embedded systems at two different levels (neuron and layer levels) and evaluates their performance in terms of makespan and energy consumption using six neural networks, both in general and in the case of CubeSats. The results show that the SNN algorithm outperforms the other two algorithms (STD and STS) and that scheduling at the layer level significantly reduces the energy consumption. Therefore, embedded systems based on multicore MCUs are suitable for executing CNNs, and they can be used, for example, on board small satellites called CubeSats.
多核 MCU 神经元和层级 CNN 调度算法
卷积神经网络(CNN)正逐步部署到嵌入式系统中,这具有挑战性,因为其计算和能源需求需要由资源和电源有限的设备来满足。例如,它们可以在物联网或边缘计算中实施,即在使用低功耗和低性能微控制器单元(MCU)的应用中实施。由于资源有限,单核 MCU 无法满足 CNN 的计算和能源需求,但多核 MCU 可以克服这些限制。本文介绍了一项实证研究,分析了在嵌入式系统上对两个不同级别(神经元和层级)的 CNN 进行调度的三种算法,并使用六个神经网络评估了它们在一般情况下和立方体卫星情况下的正常运行时间和能耗方面的性能。结果表明,SNN 算法优于其他两种算法(STD 和 STS),层级调度可显著降低能耗。因此,基于多核微控制器的嵌入式系统适用于执行 CNN,例如可用于被称为 CubeSats 的小型卫星。
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来源期刊
Microprocessors and Microsystems
Microprocessors and Microsystems 工程技术-工程:电子与电气
CiteScore
6.90
自引率
3.80%
发文量
204
审稿时长
172 days
期刊介绍: Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) is a journal covering all design and architectural aspects related to embedded systems hardware. This includes different embedded system hardware platforms ranging from custom hardware via reconfigurable systems and application specific processors to general purpose embedded processors. Special emphasis is put on novel complex embedded architectures, such as systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC) and multi-processor systems on a chip (MPSoC), as well as, their memory and communication methods and structures, such as network-on-chip (NoC). Design automation of such systems including methodologies, techniques, flows and tools for their design, as well as, novel designs of hardware components fall within the scope of this journal. Novel cyber-physical applications that use embedded systems are also central in this journal. While software is not in the main focus of this journal, methods of hardware/software co-design, as well as, application restructuring and mapping to embedded hardware platforms, that consider interplay between software and hardware components with emphasis on hardware, are also in the journal scope.
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