Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)最新文献_第2页

LFSR/SR pseudoexhaustive TPG in fewer test cycles LFSR/SR伪穷举TPG在更少的测试周期

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802878

D. Kagaris, S. Tragoudas

引用次数: 0

Soft-error detection through software fault-tolerance techniques 通过软件容错技术进行软错误检测

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802887

M. Rebaudengo, M. Reorda, Marco Torchiano, M. Violante

引用次数: 170

Determination of yield bounds prior to routing 在路由之前确定产量界限

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802863

Arunshankar Venkataraman, I. Koren

{"title":"Determination of yield bounds prior to routing","authors":"Arunshankar Venkataraman, I. Koren","doi":"10.1109/DFTVS.1999.802863","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802863","url":null,"abstract":"Integrated circuit manufacturing complexities have resulted in decreasing product yields and reliabilities. This process has been accelerated with the advent of very deep sub-micron technologies coupled with the introduction of newer materials and technologies like copper interconnects, silicon-on-insulator and increased wafer sizes. The need to improve product yields has been recognized and currently some yield enhancement techniques are used in industry CAD tools. Still, the significant increase in problem size implies that considerable time and effort can be saved if the designer could predict the yield of each design stage. In this paper we undertake an effort to derive bounds on the yield of the routing for a given placement. When the design is routed, resulting in a yield which is significantly smaller than the bound, the designer can choose to change the router cost functions, modify the placement or even re-design the unit in an attempt to increase the yield. We compare the bounds on yield obtained for a set of standard benchmarks against exact yield values for the \"vanilla\" routings, and the run times needed to calculate the two. The results indicate that reasonably good estimates of yield can be obtained in significantly lower amounts of run time. The accuracy of the estimates increases when larger designs are considered as the simplifying assumptions made and the model no longer influences the estimates significantly.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"388 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123918971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Erasure error correction with hardware detection 擦除错误纠正与硬件检测

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802896

W. Armitage, Jien-Chung Lo

{"title":"Erasure error correction with hardware detection","authors":"W. Armitage, Jien-Chung Lo","doi":"10.1109/DFTVS.1999.802896","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802896","url":null,"abstract":"Error-control coding methods have been the primary method used to protect digital communications from transmission errors. Such codes are well understood and their capabilities for error detection and correction clearly established in the literature. For correction purposes, error location is required; for this reason error-control codes' detection capabilities significantly exceed their correction capabilities. If error location information can be determined and supplied prior to processing by code-checking circuitry, such correction capability can be significantly enhanced in special circumstances. One such circumstance is that of bit \"erasures\". This work focuses on the use of undefined logic levels (near neither V/sub dd/ nor V/sub ss/) as an erasure detection method. It is shown how the error correction capabilities of error-correction codes of various d/sub min/ are enhanced by pre-detection of erasures. An implementation example is presented: this 9-bit parity-based erasure correction circuit is described; test results of the the fabricated circuit are presented as a comparison with capabilities of a simple parity checker. Specific details of extension to higher-order codes are presented.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117082036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Good processor identification in two-dimensional grids 良好的处理器识别在二维网格

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802902

F. Meyer, F. Lombardi, Jun Zhao

引用次数: 1

Power characterization of LFSRs lfsr的功率特性

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802879

Marco Brazzarola, F. Fummi

引用次数: 14

A CMOS-based logic cell for the implementation of self-checking FPGAs 一种用于实现自检fpga的基于cmos的逻辑单元

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802890

P. Lala, Anup Singh, A. Walker

引用次数: 5

Novel control pattern generators for interconnect testing with boundary scan 边界扫描互连测试控制模式的新方法

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802876

Wenyi Feng, F. Meyer, F. Lombardi

引用次数: 7

Stratified testing of multichip module systems under uneven known-good-yield 已知良率不均匀条件下多芯片模块系统的分层测试

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802885

N. Park, F. Lombardi

{"title":"Stratified testing of multichip module systems under uneven known-good-yield","authors":"N. Park, F. Lombardi","doi":"10.1109/DFTVS.1999.802885","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802885","url":null,"abstract":"In this paper, a stratified technique is proposed for testing multichip module (MCM) systems. Its advantages are an improvement in quality level (QL) and cost-effectiveness. The proposed testing approach is accomplished in the presence of uneven known-good-yield (KGY) for MCMs consisting of different sets (or strata) of chips. This approach referred to as the lowest yield-stratum first-testing (LYSFT) considers the unevenness of KGY between strata for testing the chips and improving the QL. For comparison purposes, exhaustive testing (ET), random testing (RT) and random stratified testing (RST) are also evaluated. Given the strata, KGY and the sample size of the chips under test, the proposed LYSFT approach allocates and tests the sampled chips in a greedy (first) fashion, while RT and RST select the chip (for RT) and the stratum (for RST) randomly. A Markov-chain model is developed to analyze these testing approaches and is solved analytically in O(SN/sup 3/) for the LYSFT (where S is the number of strata and N is the number of chips in the MCM). A cost model is proposed as figure of merit and shown to relate the defect level (DL) with the number of tests performed. Parametric results show that the LYSFT dramatically outperforms RT and RST for improving the QL. A considerable reduction in tests can be achieved by the LYSFT at a very small loss in QL compared with ET.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130866384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Optimal vector selection for low power BIST 低功耗BIST的最优矢量选择

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802888

Fulvio Corno, M. Reorda, M. Rebaudengo, M. Violante

引用次数: 18